鍨嬭櫉(h脿o)锛歑C6SLX45T-N3FG484C
銆�銆�绯诲垪锛歋partan-6
銆�銆�灏佽�濓細FG484
銆�銆�閫熷害绛夌礆(j铆)锛�-3
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 4.5 钀�(w脿n)鍊�(g猫) CLB锛圕onfigurable Logic Block锛�
銆�銆�濉� RAM 瀹归噺锛�2700 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細180 鍊�(g猫)
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�356 鍊�(g猫)
銆�銆�閰嶇疆妯″紡锛歋lave Serial (SPI), Master SelectMAP, Boundary Scan
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�闆绘簮闆诲�擄細Vcco = 1.8V / 2.5V / 3.3V锛孷ccint = 1.2V

XC6SLX45T-N3FG484C 鎻愪緵浜嗗挤(qi谩ng)澶х殑閭忚集鍔熻兘鍜岄潏娲荤殑閰嶇疆閬搁爡(xi脿ng)銆�
銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氬熀浜庢垚鐔熺殑 45nm 宸ヨ棟鍒堕�狅紝鍏峰倷鏇撮珮鐨勯亱(y霉n)琛岄牷鐜囧拰鏇翠綆鐨勫姛鑰�銆�
銆�銆�2. 璞愬瘜鐨勯倧杓�璩囨簮锛�4.5 钀�(w脿n)鍊�(g猫) CLB 鍙�鐢ㄤ簬瀵�(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛楅倧杓�闆昏��銆�
銆�銆�3. 鍏�(n猫i)缃�瀛樺��(ch菙)鍣�锛氭彁渚� 2700 Kb 鐨勫�� RAM锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕銆佹煡鎵捐〃绛�銆�
銆�銆�4. DSP 鏀�鎸侊��180 鍊�(g猫) DSP Slice 鏀�鎸侀珮鏁堢殑涔樻硶绱�鍔犻亱(y霉n)绠楋紝閬╁悎淇¤櫉(h脿o)铏曠悊鎳�(y墨ng)鐢�銆�
銆�銆�5. 澶氱ó I/O 妯�(bi膩o)婧�(zh菙n)锛氭敮鎸佸寘鎷� LVCMOS銆丩VDS銆丠STL 鍦ㄥ収(n猫i)鐨勫�氱ó妯�(bi膩o)婧�(zh菙n)锛屼究浜庤垏鍏朵粬瑷�(sh猫)鍌欓�ｆ帴銆�
銆�銆�6. 鍙�闈犳�э細鏀�鎸佸��(n猫i)寤鸿嚜娓�(c猫)瑭� (BIST) 鍔熻兘鍜� JTAG 閭婄晫鎺冩弿锛屾柟渚胯��(di脿o)瑭﹁垏缍�璀�(h霉)銆�
銆�銆�7. 闈堟椿鐨勯厤缃�鏂瑰紡锛氭敮鎸佸�� SPI Flash 鎴� PROM 閫�(j矛n)琛岄厤缃�锛岀��(ji菐n)鍖栭枊(k膩i)鐧�(f膩)娴佺▼銆�
銆�銆�8. 鎳�(y墨ng)鐢ㄩ牁(l菒ng)鍩熷唬娉涳細閬╃敤浜庨�氫俊銆佸伐妤�(y猫)鎺у埗銆佹秷璨�(f猫i)闆诲瓙鍙婇啱(y墨)鐧傝ō(sh猫)鍌欑瓑闋�(l菒ng)鍩�銆�

瑭插瀷铏�(h脿o)鐨� FPGA 鍙�鎳�(y墨ng)鐢ㄤ簬浠ヤ笅鍫�(ch菐ng)鏅�锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)閫氫俊锛氬��(sh铆)鐝�(xi脿n)楂橀�熸暩(sh霉)鎿�(j霉)鍌宠几鍗�(xi茅)璀扮殑鐗╃悊灞ゅ拰閺堣矾灞ゅ姛鑳�銆�
銆�銆�2. 瑕栭牷铏曠悊锛氶��(j矛n)琛屽湒鍍忕府鏀�銆佹牸寮忚綁(zhu菐n)鎻涘拰鐗规晥鐢熸垚绛夋搷浣溿��
銆�銆�3. 宓屽叆寮忕郴绲�(t菕ng)锛氫綔鐐轰富鎺ц姱鐗囧畬鎴愬��(sh铆)鏅�(sh铆)鎺у埗鍜屾暩(sh霉)鎿�(j霉)铏曠悊浠诲嫏(w霉)銆�
銆�銆�4. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細妲�(g貌u)寤� PLC 鎴栭亱(y霉n)鍕�(d貌ng)鎺у埗鍣ㄧ殑鏍稿績閮ㄥ垎銆�
銆�銆�5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鐢ㄤ簬瓒呰伈娉㈡垚鍍�銆佸績闆诲湒鍒嗘瀽绛夊剙鍣ㄧ殑淇¤櫉(h脿o)铏曠悊閮ㄥ垎銆�
銆�銆�6. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細鏀�鎸侀煶闋昏В纰�銆佽�栭牷绶ㄨВ纰肩瓑鍔熻��銆�
銆�銆�鐢变簬鍏堕珮鎬ц兘鍜岄潏娲绘��锛孹C6SLX45T-N3FG484C 鎴愮偤鐪惧�氬伐绋嬪斧鍦ㄨ��(sh猫)瑷�(j矛)涓�灏忓�� FPGA 绯荤当(t菕ng)鏅�(sh铆)鐨勯�栭伕鏂规�堛��

XC6SLX45T-3FG484C, XC6SLX45T-2FG484C