鏅傞枔锛�2025/6/4 10:36:02
闁辫畝锛�6
XCZU2CG-1SFVC784I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪涓殑 FPGA 鑺墖锛屽熀浜庡厛閫茬殑 FinFET 宸ヨ棟鍒堕��銆傝┎鑺墖閬╃敤浜庨珮鎬ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熷拰宸ユキ(y猫)鑷嫊鍖栫瓑鎳夌敤闋樺煙銆傚叾鍏�(n猫i)閮ㄩ泦鎴愪簡澶ч噺鐨勯倧杓柈鍏�銆丏SP Slice 鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒冲京闆滆ō瑷堢殑闇�姹�銆�
銆�銆�姝ゅ瀷铏熷爆浜� Zynq UltraScale+ MPSoC 绯诲垪锛屽叿鏈夊挤澶х殑鍙法绋嬮倧杓兘鍔涗互鍙婄‖鍖栫殑铏曠悊鍣ㄧ郴绲�(t菕ng)锛屾敮鎸佸鏅傝檿鐞嗚垏闈堟椿鐨勭‖浠跺姞閫熺祼(ji茅)鍚�銆傚悓鏅�锛屽畠閭勫叿鍌欎綆鍔熻�楃壒鎬�锛岄仼鍚堝皪鎬ц兘鍜屽姛鑰楀潎鏈夊毚鏍艰姹傜殑鎳夌敤鍫存櫙銆�
宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 1300
銆�銆�濉� RAM 鏁�(sh霉)閲忥細绱� 1200
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細澶氶仈 240
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂� 28Gbps
銆�銆�閰嶇疆妯″紡锛歁aster SPI, Slave SPI, JTAG
銆�銆�灏佽褰㈠紡锛歋FVC784
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
XCZU2CG-1SFVC784I 鐨勪富瑕佺壒鎬у寘鎷珮搴﹂泦鎴愮殑鍙法绋嬮倧杓硣婧愬拰纭寲妯″锛屼緥濡� ARM Cortex-A53 铏曠悊鍣ㄥ瓙绯荤当(t菕ng)锛屽彲鐢ㄤ簬閬嬭宓屽叆寮忔搷浣滅郴绲�(t菕ng)銆�
銆�銆�姝ゅ锛屽畠閭勬彁渚涢潏娲荤殑娣峰悎绮惧害娴粸閬嬬畻鏀寔锛岄仼鐢ㄤ簬娣卞害瀛哥繏鎺ㄧ悊鍜屽叾浠栭珮鍚炲悙閲忚▓绠椾换鍕欍��
銆�銆�瑭插櫒浠剁殑鏀剁櫦(f膩)鍣ㄦ敮鎸佸绋崝(xi茅)璀版婧栵紝濡� PCIe Gen3/Gen4銆丆CIX 鍜屼互澶恫(w菐ng)绛�锛屽緸鑰岀啊鍖栦簡绯荤当(t菕ng)绱氱殑瑷▓娴佺▼銆�
銆�銆�鐐轰簡闄嶄綆鏁撮珨鍔熻��锛孹CZU2CG 鎻愪緵浜嗗嫊鎱�(t脿i)闆绘簮绠＄悊鍔熻兘锛屽厑瑷辨牴鎿�(j霉)瀵﹂殯璨犺級鎯呮硜瑾�(di脿o)鏁磋姱鐗囩殑宸ヤ綔鐙�鎱�(t脿i)銆�
銆�銆�鏈�鍚庯紝閫氶亷閲囩敤楂樼礆灏佽鎶�琛�锛岀⒑淇濅簡淇¤櫉瀹屾暣鎬у拰鏁ｇ啽鎬ц兘鐨勫劒(y艒u)鍖�銆�
XCZU2CG-1SFVC784I 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘鍜岄潏娲绘�х殑闋樺煙銆傚吀鍨嬫噳鐢ㄥ寘鎷絾涓嶉檺浜庯細
銆�銆�1. 鏈夌窔鍜岀劇绶氶�氫俊鍩虹瑷柦瑷倷锛屼緥濡傚熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜庢暩(sh霉)鎿�(j霉)搴煡瑭�銆佽闋昏綁(zhu菐n)纰煎拰缍�(w菐ng)绲″畨鍏ㄧ瓑鍔熻兘銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忚ō鍌欎腑鐨勫湒鍍忚檿鐞嗗拰鏁�(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�4. 姹借粖椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛変腑鐨勫偝鎰熷櫒铻嶅悎鍜屾焙绛栨帶鍒�銆�
銆�銆�5. 宸ユキ(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂滃拰閭婄罚瑷堢畻绡�(ji茅)榛�锛屾彁渚涙湰鍦版櫤鑳藉垎鏋愯兘鍔�銆�
銆�銆�6. 楂樼娓│娓噺鍎�鍣�锛屽绀烘尝鍣ㄥ拰闋昏瓬鍒嗘瀽鍎�銆�
XCZU3EG-1SFVC784I
銆�銆�XCZU4EV-1SFVC784I
銆�銆�XCZU5EV-1FFVC1156I
