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鐢�(ch菐n)鍝佸瀷铏�	XC7K410T-2FFG900I
鎻忚堪	IC FPGA 500 I/O 900FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Kintex?-7
閮ㄥ垎鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.97V~1.03V
宸ヤ綔婧害	-40掳C~100掳C(TJ)
鍖�/绠�	900-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	900-FCBGA(31x31)
鍩虹(ch菙)閮ㄤ欢铏�	XC7K410T

鐢�(ch菐n)鍝佸湒鐗�

XC7K410T-2FFG900I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅傞悩闋荤巼-鏈€澶у€�	1286.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.61 ns
JESD-30浠ｇ⒓	S-PBGA-B900
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	29306880
CLB鏁�(sh霉)閲�	31775.0
杓稿叆鏁�(sh霉)閲�	500.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	406720.0
杓稿嚭鏁�(sh霉)閲�	500.0
绲傜鏁�(sh霉)閲�	900
绲勭箶	31775 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	鏈(bi膩o)鏄�
闆绘簮	1,1.8,3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	3.35姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.0 V
闆绘簮闆诲-鏈€灏忓€�	0.97 V
闆绘簮闆诲-鏈€澶у€�	1.03 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn96.5Ag3.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	鏈(bi膩o)鏄�
闀峰害	31.0姣背
瀵害	31.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍逛唬纰�	BGA900,30X30,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	FBGA-900

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS妯�(bi膩o)婧�(zh菙n)
婵曞害鏁忔劅搴︾瓑绱�(MSL)	4(72灏忔檪)

鐗归粸(di菐n)

36 Kb闆欑鍙lock RAM锛屽収(n猫i)缃瓼IFO閭忚集锛岀敤浜庣墖涓婃暩(sh霉)鎿�(j霉)绶╂矕銆�
楂樻€ц兘SelectIO?鎶€琛�(sh霉)锛屾敮鎸侀珮閬�(d谩)1,866 Mb / s鐨凞DR3鎺ュ彛銆�
PCIExpress?(PCIe)闆嗘垚妯″锛屾渶澶氬彲鏀寔x8 Gen3绔粸(di菐n)鍜屾牴绔彛瑷�(sh猫)瑷�銆�
鍩轰簬鐪熷6杓稿叆鏌ユ壘琛�(LUT)鎶€琛�(sh霉)鐨勯珮绱氶珮鎬ц兘FPGA閭忚集锛屽彲閰嶇疆鐐哄垎甯冨紡瀛樺劜鍣�銆�
鐢ㄦ埗鍙厤缃殑妯℃摤鎺ュ彛(XADC)锛屽寘鍚付鏈夌墖涓婄啽鍜岄浕婧愬偝鎰熷櫒鐨勯洐12浣�1MSPS妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒銆�
DSP鐗囧叿鏈�25 x 18涔樻硶鍣�锛�48浣嶇疮鍔犲櫒鍜岄爯(y霉)鍔犳硶鍣紝鐢ㄤ簬楂樻€ц兘婵炬尝锛屽寘鎷劒(y艒u)鍖栫殑灏嶇ū绯绘暩(sh霉)婵炬尝銆�
寮�(qi谩ng)澶х殑鏅傞悩绠＄悊纾佽布(CMT)锛岀祼(ji茅)鍚堥帠鐩哥挵(hu谩n)(PLL)鍜屾贩鍚堟ā寮忔檪閻樼鐞嗗櫒(MMCM)妯″锛屽鐝�(xi脿n)楂樼簿搴﹀拰浣庢姈鍕�銆�
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