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XC7A75T-L2CSG324E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囦腑鐨勪竴鍊嬪瀷铏熴�侫rtix-7 绯诲垪鏄熀浜� 28nm 宸ヨ棟鎶�琛撶殑楂樻�ц兘 FPGA锛屽叿鏈変綆鍔熻��銆侀珮闆嗘垚搴﹀拰闈堟椿鎬х殑鐗归粸锛岄仼鐢ㄤ簬澶氱ó寰╅洔鐨勬噳鐢ㄥ牬鏅�傝┎鍨嬭櫉閲囩敤 CSG324 灏佽褰㈠紡锛岄仼鍚堥渶瑕佷腑绛夐倧杓硣婧愪笖灏嶆�ц兘鏈変竴瀹氳姹傜殑鎳夌敤鍫村悎銆�
銆�銆�Artix-7 绯诲垪 FPGA 鎻愪緵浜嗚睈瀵岀殑鍔熻兘妯″锛屽寘鎷� DSP Slice銆丅lock RAM銆佹暩(sh霉)瀛楁檪閻樼鐞嗗櫒锛圖CM/PLL锛�銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑锛屽苟鏀寔澶氱ó鎺ュ彛妯欐簴锛屽 PCIe銆丏DR3 鍜屽崈鍏嗕互澶恫(w菐ng)绛夈��
鍨嬭櫉锛歑C7A75T-L2CSG324E
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍝佺墝锛歑ilinx
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�FPGA閭忚集鍠厓鏁�(sh霉)閲忥細75K
銆�銆�RAM瀹归噺锛�1.5Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細180
銆�銆�I/O寮曡叧鏁�(sh霉)锛�216
銆�銆�灏佽椤炲瀷锛欳SG324
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SPI
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛�0.9V 鏍稿績闆诲锛�1.0V 杓斿姪闆诲锛�1.8V I/O闆诲
XC7A75T-L2CSG324E 鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氶噰鐢� UltraScale 鏋舵锛屾敮鎸侀珮閬� 640 Mb/s 鐨勫収(n猫i)閮ㄤ簰鑱�(li谩n)甯跺銆�
銆�銆�2. 浣庡姛鑰楄ō瑷堬細閫氶亷 PowerGating 鎶�琛撳拰鍕曟厠(t脿i)闆绘簮绠＄悊鍔熻兘鏈夋晥闄嶄綆闈滄厠(t脿i)鍔熻�楀拰鍕曟厠(t脿i)鍔熻�椼��
銆�銆�3. 闈堟椿鐨� I/O 鏀寔锛氭彁渚涘閬� 216 鍊嬬敤鎴� I/O 寮曡叧锛屽吋瀹瑰绋浕骞虫婧栥��
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銆�銆�5. 楂橀�熶覆琛屾帴鍙ｏ細鏀寔楂橀仈 6.6 Gbps 鐨� GTX 鏀剁櫦(f膩)鍣ㄩ�熺巼锛岄仼閰嶅悇绋珮閫熼�氫俊鍗�(xi茅)璀�銆�
銆�銆�6. 鍙潬鎬ц垏瀹夊叏鎬э細鎻愪緵鍔犲瘑姣旂壒娴�銆丄ES-256 鍔犲瘑浠ュ強 CRC 閷妾㈡脯鍔熻兘锛岀⒑淇濇暩(sh霉)鎿�(j霉)鍌宠几?sh霉)闄岃俯顐嶆荡?/p>
XC7A75T-L2CSG324E 鑺墖寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佸皬鍨嬭渹绐╃恫(w菐ng)绲¤ō鍌�銆佸厜鍌宠几妯″绛夈��
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鎺у埗銆佸湒鍍忚檿鐞嗐�侀亱鍕曟帶鍒剁瓑銆�
銆�銆�3. 閱�(y墨)鐧傞浕瀛愶細鏀寔瓒呰伈娉㈣ō鍌欍�丆T鎺冩弿鍎�銆佸収(n猫i)绐洪彙绛夐啱(y墨)鐧傛垚鍍忕郴绲�(t菕ng)銆�
銆�銆�4. 姹借粖闆诲瓙锛氬彲鐢ㄤ簬楂樼礆椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛夈�佷俊鎭妯傜郴绲�(t菕ng)浠ュ強杌婅級缍�(w菐ng)绲�銆�
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銆�銆�6. 宓屽叆寮忚▓绠楋細浣滅偤宓屽叆寮忚檿鐞嗗櫒鐨勫崝(xi茅)铏曠悊鍣紝鐢ㄤ簬鍔犻�熺壒瀹氱畻娉曟垨浠诲嫏銆�
XC7A75T-2CSG324C,XC7A75T-2FGG484I,XC7A75T-2FGG484E
