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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU15EG-1FFVC900E

XCZU15EG-1FFVC900E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/25 14:21:59 鏌ョ湅 闁辫畝锛�55

XCZU15EG-1FFVC900E 鏄竴娆惧熀浜� Xilinx UltraScale+ 鏋舵(g貌u)鐨勯珮鎬ц兘 FPGA 鑺墖锛屽爆浜� Zynq UltraScale+ MPSoC 绯诲垪銆傝┎绯诲垪鑺墖闆嗘垚浜� ARM Cortex-A53 铏曠悊鍣ㄥ拰瀵�(sh铆)鏅�(sh铆)铏曠悊鍠厓锛圧PU锛�锛屽苟绲�(ji茅)鍚堜簡鍙法绋嬮倧杓紙PL锛夐儴鍒嗭紝浣垮叾閬╃敤浜庨渶瑕侀珮鎬ц兘瑷�(j矛)绠�銆佸(sh铆)鏅�(sh铆)鎺у埗鍜岄潏娲荤‖浠跺姞閫熺殑鎳�(y墨ng)鐢ㄥ牬鏅��
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鍙冩暩(sh霉)

灏佽锛欶FVC900
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O 鏁�(sh霉)閲忥細2600
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�
銆�銆�瀛樺劜瀹归噺锛�8.4Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細4800
銆�銆�鏌ユ壘琛紙LUTs锛夋暩(sh霉)閲忥細绱� 95 钀��(g猫)
銆�銆�鍏�(n猫i)閮ㄦ檪(sh铆)閻樼鐞嗭細鏀寔 PLL 鍜� MMCM
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲鏍规摎(j霉)鍏烽珨 Bank 鍙(di脿o)

鐗规��

XCZU15EG-1FFVC900E 鎻愪緵浜嗗挤(qi谩ng)澶х殑鐣版(g貌u)铏曠悊鑳藉姏锛屽寘鍚洓鏍� ARM Cortex-A53 鎳�(y墨ng)鐢ㄨ檿鐞嗗櫒鍜岄洐鏍� ARM Cortex-R5 瀵�(sh铆)鏅�(sh铆)铏曠悊鍣�銆傚叾鍙法绋嬮倧杓儴鍒嗗叿鏈夐珮搴﹂潏娲绘��锛屽彲浠ュ(sh铆)鐝�(xi脿n)瀹氬埗鍖栫殑纭欢鍔犻�熷姛鑳�銆�
銆�銆�姝ゅ锛岃姱鐗囬倓鏀寔楂橀�熸敹鐧�(f膩)鍣紙閫熺巼鍙仈(d谩) 32.75Gbps锛�锛屾彁渚涘绋帴鍙ｉ伕闋�(xi脿ng)锛屽 PCIe Gen4銆乁SB 3.0 鍜屽崈鍏嗕互澶恫(w菐ng)绛�銆傝姱鐗囩殑鍔熻�楀劒(y艒u)鍖栨妧琛�(sh霉)浣垮緱鍏跺湪楂樻�ц兘閬�(y霉n)绠楃殑鍚屾檪(sh铆)鑳藉淇濇寔杓冧綆鐨勮兘鑰楁按骞炽��
銆�銆�瀹夊叏鎬ф柟闈�锛孹CZU15EG 鏀寔 AES 鍜� RSA 绛夊姞瀵嗘(bi膩o)婧�(zh菙n)锛岀⒑淇濇暩(sh霉)鎿�(j霉)鍌宠几鍜屽瓨鍎茬殑瀹夊叏鎬�銆傚悓鏅�(sh铆)锛屽畠閭勫叿鍌欓尟(cu貌)瑾ゆ娓垏绯炬锛圗CC锛夊姛鑳�锛屽寮�(qi谩ng)浜嗙郴绲�(t菕ng)鐨勫彲闈犳�у拰绌�(w臎n)瀹氭��銆�
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瑭茶姱鐗囬仼鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 楂橀�熼�氫俊瑷�(sh猫)鍌�锛屽鍩虹珯鍜岃矾鐢卞櫒涓殑淇¤櫉铏曠悊妯″銆�
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銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌欎腑鐨勫湒鍍忚檿鐞嗗紩鎿�銆�
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銆�銆�6. 鑸┖鑸ぉ闋�(l菒ng)鍩熺殑椋涜鎺у埗绯荤当(t菕ng)鍜屽皫(d菐o)鑸柈鍏冦��

鏇夸唬鍨嬭櫉

XCZU15EG-2FFVC900E
銆�銆�XCZU15EV-1FFVC1517E
銆�銆�XCZU15EV-2FFVC1517E

xczu15eg-1ffvc900e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 渚涙噳(y墨ng)鍟�
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  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児(ji脿)

xczu15eg-1ffvc900e鍙冩暩(sh霉)

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  • 鍍�(ji脿)鏍�1 : 锟�33,324.72000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
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  • RAM 澶у皬256KB
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  • 灏佽/澶栨900-BBGA锛孎(xi脿n)CBGA
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