鍨嬭櫉(h脿o)锛歑CVU3P-1FFVC1517
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�FPGA绯诲垪锛歎ltraScale+
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 300 钀�(w脿n)鍊�(g猫)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細~2880鍊�(g猫)
銆�銆�RAM 璩囨簮锛殈22MB
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1440 鍊�(g猫)
銆�銆�閰嶇疆妯″紡锛歋electMAP, Master SPI, Slave SPI
銆�銆�宸ヤ綔闆诲�擄��0.85V 鏍搁浕澹�锛�1.0V 杓斿姪闆诲��
銆�銆�灏佽�濋��(l猫i)鍨嬶細FFVC1517
銆�銆�鏈�澶ф檪(sh铆)閻橀牷鐜囷細瓒呴亷(gu貌) 500MHz

XCVU3P-1FFVC1517 鎿佹湁浠ヤ笅闂�(gu膩n)閸电壒鎬э細
銆�銆�1. 楂樻�ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氶噰鐢� UltraScale+ 鏋舵��(g貌u)锛屾彁渚涙洿楂樻晥鐨勮矾鐢卞拰鏇撮珮鐨勫悶鍚愰噺銆�
銆�銆�2. 鍏�(n猫i)缃� HBM 鏀�鎸侊細閮ㄥ垎鍨嬭��(h脿o)鏀�鎸侀珮甯跺��鍏�(n猫i)瀛� (HBM)锛屾彁渚涙サ楂樼殑鏁�(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�3. 寮�(qi谩ng)澶х殑 DSP 鍔熻兘锛氶厤鍌欏ぇ閲� DSP Slice锛岄仼鐢ㄤ簬娴�榛�(di菐n)閬�(y霉n)绠楀拰淇¤櫉(h脿o)铏曠悊浠诲嫏(w霉)銆�
銆�銆�4. 澶氭ǎ鍖栫殑鎺ュ彛锛氭敮鎸侀珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岄�熺巼楂橀仈(d谩) 32.75Gbps锛屽苟鍏煎�� PCIe Gen4 鍜� CCIX 鍗�(xi茅)璀�銆�
銆�銆�5. 瀹夊叏鎬у�炲��(qi谩ng)锛氭彁渚� AES-256 鍜� SHA-256 鍔犲瘑鍔熻兘锛岀⒑淇� IP 鍜屾暩(sh霉)鎿�(j霉)鐨勫畨鍏ㄦ��銆�
銆�銆�6. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氫娇鐢� 16nm FinFET 宸ヨ棟锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅�(sh铆)闄嶄綆鍔熻��銆�
銆�銆�7. 鏄撶敤鎬у挤(qi谩ng)锛氶�氶亷(gu貌) Vivado 宸ュ叿閺堢啊(ji菐n)鍖栭枊(k膩i)鐧�(f膩)娴佺▼锛屽苟鎻愪緵璞愬瘜鐨� IP 鏍稿拰鍙冭�冭ō(sh猫)瑷�(j矛)銆�

瑭� FPGA 鍨嬭櫉(h脿o)寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細鐢ㄤ簬鏁�(sh霉)鎿�(j霉)搴�(k霉)鏌ヨ��(x煤n)鍎�(y艒u)鍖�銆丄I 鎺ㄧ悊鍔犻�熷拰缍�(w菐ng)绲�(lu貌)瀹夊叏铏曠悊銆�
銆�銆�2. 缍�(w菐ng)绲�(lu貌)閫氫俊锛氭敮鎸� 5G 鍩虹珯銆佹牳蹇冪恫(w菐ng)闂�(gu膩n)鍜岃矾鐢卞櫒鐨勯枊(k膩i)鐧�(f膩)銆�
銆�銆�3. 瑕栭牷铏曠悊锛氶仼鐢ㄤ簬 4K/8K 瑕栭牷绶ㄨВ纰煎拰鍦栧儚鍒嗘瀽銆�
銆�銆�4. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細鐢ㄤ簬瀵�(sh铆)鏅�(sh铆)鎺у埗鍜岄珮绮惧害鏁�(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細鎻愪緵蹇�閫熷湒鍍忛噸寤哄拰瑷烘柗杓斿姪鍔熻兘銆�
銆�銆�6. 鑸�绌鸿埅澶╄垏鍦�(gu贸)闃诧細婊�(m菐n)瓒冲毚(y谩n)鑻涚挵(hu谩n)澧冧笅鐨勪俊铏�(h脿o)铏曠悊鍜岄�氫俊闇�姹傘��

XCVU9P-2FFVA2104, XCVU5P-2FFVC1517E