鏅傞枔锛�2025/5/12 15:28:35
闁辫畝锛�24
XCVU095-2FFVD1924I 鏄� Xilinx锛堣辰闈堟�濓級鎺ㄥ嚭鐨� UltraScale 绯诲垪 FPGA 鑺墖銆傝┎鑺墖鍩轰簬 20nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮瀵嗗害閭忚集鍠厓鍜岃睈瀵岀殑鍙法绋嬭硣婧�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊鍩虹瑷柦銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熴�佸湒鍍忚檿鐞嗕互鍙婅埅绌鸿埅澶╃瓑闋樺煙銆�
銆�銆�姝ゅ瀷铏熷爆浜� Virtex UltraScale 绯诲垪涓殑楂樼鐢�(ch菐n)鍝侊紝鏀寔澶氱ó楂橀�熸帴鍙ｅ拰鍗�(xi茅)璀�锛屽苟涓旈泦鎴愪簡澶у閲忕殑宓屽叆寮忓瓨鍎插櫒鍜� DSP 妯″锛屾豢瓒冲京闆滅郴绲�(t菕ng)瑷▓鐨勯渶姹�銆�
绯诲垪锛歏irtex UltraScale
銆�銆�宸ヨ棟鍒剁▼锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 95K
銆�銆�鏌ユ壘琛紙LUTs锛夛細瓒呴亷 570K
銆�銆�瑙哥櫦(f膩)鍣細瓒呴亷 1.1M
銆�銆�DSP Slice 鏁�(sh霉)閲忥細5880
銆�銆�Block RAM 瀹归噺锛�68MB
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1530
銆�銆�灏佽椤炲瀷锛欶FG1924
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛氬鏍搁浕婧愭灦妲�
XCVU095-2FFVD1924I 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘��銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓祼妲嬶紝鑳藉?q奴)宕縁(xi脿n)寰╅洔鐨勭畻娉曞拰鏁�(sh霉)鎿�(j霉)璺緫銆�
銆�銆�2. 鍏�(n猫i)缃ぇ閲� DSP 妯″锛岄潪甯搁仼鍚堢敤浜庝俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 鏀寔楂橀仈 32.75Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛岄仼鎳夋渶鏂扮殑閫氫俊妯欐簴銆�
銆�銆�4. 寮峰ぇ鐨勫祵鍏ュ紡瀛樺劜鍣ㄨ硣婧�锛屽 Block RAM 鍜屽垎甯冨紡 RAM锛屽劒(y艒u)鍖栦簡鏁�(sh霉)鎿�(j霉)绶╁瓨鍔熻兘銆�
銆�銆�5. 鍏堥�茬殑鏅傞悩绠＄悊鍜屼綆鍔熻�楁妧琛擄紝纰轰繚楂樻晥閬嬭銆�
銆�銆�6. 鏀寔 PCIe Gen3/Gen4銆佷互澶恫(w菐ng) MAC銆両nterlaken 绛夊父鐢ㄦ帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�7. 鍙�氶亷 JTAG 鎴� SelectMAP 鎺ュ彛閫茶閰嶇疆銆�
銆�銆�8. 闆嗘垚寮峰ぇ鐨勮(di脿o)瑭﹀拰鐩�(ji膩n)鎺у伐鍏�锛岀啊鍖栭枊鐧�(f膩)娴佺▼銆�
閫欐 FPGA 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜庢彁鍗囨湇鍕欏櫒鎬ц兘銆�
銆�銆�2. 鐒＄窔閫氫俊鍩虹珯锛屼緥濡� LTE 鍜� 5G 缍�(w菐ng)绲¤ō鍌�銆�
銆�銆�3. 楂橀�熸暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗙郴绲�(t菕ng)銆�
銆�銆�4. 瑕栭牷寤ｆ挱鍜屽湒鍍忚檿鐞嗗钩鑷�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忚ō鍌�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栨帶鍒跺拰姗熷櫒浜烘妧琛�銆�
銆�銆�7. 鑸┖鑸ぉ鍙婂湅闃茬浉闂滈爡鐩��
銆�銆�鐢变簬鍏堕珮搴︾殑鍙法绋嬫�у拰寮峰ぇ鐨勮檿鐞嗚兘鍔涳紝XCVU095 鎴愮偤瑷卞楂樻�ц兘鎳夌敤鍫存櫙鐨勭悊鎯抽伕鎿�銆�
XCVU095-1FFVD1924E
銆�銆�XCVU095-2FFVA2104E
銆�銆�XCVU095-2FFVA2104I
銆�銆�XCVU095-3FFVD1924E
