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XCKU13P-2FFVE900 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖锛岃┎绯诲垪鍣ㄤ欢閲囩敤 16nm FinFET 鍒剁▼宸ヨ棟鍒堕�狅紝鍏锋湁楂橀泦鎴愬害鍜岄珮鎬ц兘鐗归粸銆傛鍨嬭櫉閬╃敤浜庨渶瑕佸京闆滈倧杓亱绠椼�侀珮閫熶俊铏熻檿鐞嗗強澶ц(gu墨)妯℃暩鎿氬偝杓哥殑鎳夌敤鍫存櫙锛屽閫氫俊鍩虹瑷柦銆佹暩鎿氫腑蹇冨姞閫熷櫒浠ュ強楂樼宓屽叆寮忕郴绲�(t菕ng)銆�
銆�銆�瑭茶姱鐗囨彁渚涗簡璞愬瘜鐨� DSP Slice 鍜� Block RAM 璩囨簮锛屽苟鏀寔澶氱ó涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼閰嶇疆锛屾豢瓒充笉鍚岃ō瑷堥渶姹�銆傚叾灏佽褰㈠紡鐐� FFVE900锛岃兘澶犳湁鏁堟彁鍗囨暎鐔辨�ц兘骞堕仼鎳夎嫑鍒荤殑宸ヤ綔鐠�(hu谩n)澧�銆�
鍨嬭櫉锛歑CKU13P-2FFVE900
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欿intex UltraScale
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�FPGA Logic Cells锛氱磩 47.5K
銆�銆�DSP Slices锛氱磩 2880
銆�銆�Block RAM锛氱磩 2970 Kb
銆�銆�鐢ㄦ埗 Flash Memory锛氱磩 7.5 Mb
銆�銆�I/O 鏁搁噺锛氭渶澶ф敮鎸� 744
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄦ暩閲忥細16 灏�
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樻敮鎸� 16.3 Gbps
銆�銆�渚涢浕闆诲锛�0.9V 鏍稿績闆诲锛�1.0V I/O 闆诲
銆�銆�灏佽椤炲瀷锛欶FVE900
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCKU13P-2FFVE900 鎿佹湁寮峰ぇ鐨勫彲绶ㄧ▼閭忚集璩囨簮鍜岄珮鏁堢殑浜掗�ｆ灦妲�锛屾敮鎸侀潏娲荤殑 IP 闆嗘垚鑸囨ā濉婂寲瑷▓銆傚叾鍏х疆鐨� UltraRAM 鎶�琛撴彁渚涘ぇ瀹归噺鐗囦笂瀛樺劜锛屾笡灏戝皪澶栭儴瀛樺劜鍣ㄧ殑渚濊炒锛屽悓鏅傞檷浣庡姛鑰楀拰寤堕伈銆傛澶栵紝瑭茶姱鐗囬倓鍏峰倷楂樼礆闆绘簮绠＄悊鍔熻兘锛屽彲鏍规摎瀵﹂殯璨犺級鍕曟厠(t脿i)瑾挎暣闆诲鍜岄牷鐜�锛屽劒(y艒u)鍖栨暣楂旇兘鑰楄〃鐝�銆�
銆�銆�鍦ㄥ畨鍏ㄦ�ф柟闈�锛孹CKU13P-2FFVE900 鏀寔 AES-256 鍔犲瘑绠楁硶淇濊浣嶆祦鏁告摎锛屽苟閫氶亷纭欢淇′换鏍规鍒堕槻姝㈡儭鎰忕鏀规垨鍏嬮殕銆傚皪浜庢檪閻樼鐞�锛屽畠闆嗘垚浜嗗璺� PLL 鍜� MMCM锛堟贩鍚堟ā寮忔檪閻樼鐞嗗櫒锛�锛岀⒑淇濈簿纰虹殑鏅傞悩鍒嗛牷鑸囩浉浣嶆帶鍒躲�傞�欎簺鍎�(y艒u)鍕娇鍏舵垚鐐烘寤轰笅涓�浠ｉ珮鎬ц兘瑷堢畻骞宠嚭鐨勭悊鎯抽伕鎿�銆�
XCKU13P-2FFVE900 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷 - 鍖呮嫭鍩虹珯鎺у埗鍣ㄣ�佽矾鐢卞櫒浜ゆ彌鐭╅櫍绛�锛屽埄鐢ㄥ叾楂樺悶鍚愰噺鐗规�у鐝惧京闆滅殑鍗�(xi茅)璀版＇瑙ｆ瀽鑸囨祦閲忚搴�銆�
銆�銆�2. 鏁告摎涓績 - 鐢ㄤ綔鏈嶅嫏鍣ㄥ嵏杓夊紩鎿庢垨 AI 鎺ㄧ悊鍔犻�熷崱鐨勬牳蹇冪祫浠�锛屾彁鍗囧柈浣嶅姛鑰椾笅鐨勭畻鍔涘瘑搴�銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖� - 鎻愪緵瀵︽檪淇¤櫉閲囬泦鑸囨帶鍒惰兘鍔�锛岄仼閰嶆鍣ㄤ汉瑕栬鎴栧叾浠栫簿瀵嗘脯閲忎换鍕�銆�
銆�銆�4. 閱�(y墨)鐧傚奖鍍� - 鍦� CT 鎺冩弿鍎�銆佽秴鑱叉尝瑷烘柗鍎�涓矤璨湒鍍忛噸寤虹畻娉曠殑纭欢鍔犻�燂紝淇濊瓑姣绱氶熆鎳夋檪闁�銆�
銆�銆�5. 鑸┖鑸ぉ - 鍙冭垏鏄熻級瑷堢畻姗熸垨鑰呭皫鑸浄閬旂郴绲�(t菕ng)鐨勯枊鐧�(f膩)锛岀稉鍙椾綇妤电楂樹綆婧惊鐠�(hu谩n)鑰冮銆�
XCKU13P-1FFVE900
銆�銆�XCKU13P-3FFVE900
