XCVU125-2FLVB1760I 鏅傞枔锛�2023/11/13 17:11:56 闁辫畝锛�209

XCVU125-2FLVB1760I FPGA 鏋舵(g貌u)鐢遍珮鎬ц兘 FPGA 鍜� MPSoC 绯诲垪绲勬垚锛屽彲婊胯冻寤ｆ硾鐨勭郴绲�(t菕ng)瑕佹眰锛岄噸榛炴槸閫氶亷鐪惧鍓�(chu脿ng)鏂版妧琛�(sh霉)閫叉闄嶄綆绺藉姛鑰�銆�

姒傝堪

    XCVU125-2FLVB1760I FPGA娉ㄩ噸鎬у児姣�锛岄噰鐢ㄥ柈鐗囧拰涓嬩竴浠ｅ爢鐤婄浜掗€� (SSI) 鎶€琛�(sh霉)銆� 楂� DSP 鍜屽 RAM 閭忚集姣斾互鍙婁笅涓€浠ｆ敹鐧�(f膩)鍣ㄨ垏浣庢垚鏈皝瑁濈浉绲�(ji茅)鍚�锛屽鐝�(xi脿n)浜嗗姛鑳藉拰鎴愭湰鐨勬渶浣崇祼(ji茅)鍚堛€�
    Kintex UltraScale+ FPGA锛氶€欎簺 XCVU125-2FLVB1760I 鍣ㄤ欢鍩轰簬 UltraScale 鏋舵(g貌u)锛屽叿鏈夋洿楂樼殑鎬ц兘鍜岀墖涓� UltraRAM 瀛樺劜鍣�锛屽彲闄嶄綆 BOM 鎴愭湰锛屾彁渚涢珮鎬ц兘澶栬ō(sh猫)鍜岀稉(j墨ng)婵熼珮鏁堢殑绯荤当(t菕ng)瀵︽柦鐨勭悊鎯崇祫鍚�銆� 姝ゅ锛孠intex UltraScale+ FPGA 鍏锋湁澶氱ó闆绘簮閬搁爡锛屽彲鍦ㄦ墍闇€鐨勭郴绲�(t菕ng)鎬ц兘鍜屾渶灏忓姛鐜囪寖鍦嶄箣闁撳鐝�(xi脿n)鏈€浣冲钩琛�銆�
    Virtex UltraScale+ FPGA锛氶€欎簺鍣ㄤ欢鍩轰簬 UltraScale 鏋舵(g貌u)锛屽叿鏈夋キ(y猫)鐣屾渶楂樼殑鏀剁櫦(f膩)鍣ㄥ付瀵�銆佹渶楂樼殑 DSP 鏁�(sh霉)閲忓拰鏈€楂樼殑鐗囦笂鍏�(n猫i)瀛�锛屽彲瀵︾従(xi脿n)绲傛サ绯荤当(t菕ng)鎬ц兘銆� 姝ゅ锛孷irtex UltraScale+ FPGA 閭勬彁渚涘绋浕婧愰伕闋�锛屽彲鍦ㄦ墍闇€鐨勭郴绲�(t菕ng)鎬ц兘鍜屾渶灏忓姛鑰椾箣闁撳鐝�(xi脿n)鏈€浣冲钩琛°€�
    XCVU125-2FLVB1760I 鎻愪緵鍓嶆墍鏈湁鐨勭瘈(ji茅)鑳�銆佽檿鐞�銆佸彲绶ㄧ▼鍔犻€熴€両/O 鍜屽収(n猫i)瀛樺付瀵�锛岄潪甯搁仼鍚堥渶瑕佺暟妲�(g貌u)铏曠悊鐨勬噳(y墨ng)鐢�銆�

鍙冩暩(sh霉)

    绯诲垪:XCVU125
    閭忚集鍏冧欢鏁�(sh霉)閲�:1566600 LE
    鑷仼鎳�(y墨ng)閭忚集妯″ - ALM:89520 ALM
    宓屽叆寮忓収(n猫i)瀛�:88.6 Mbit
    杓稿叆/杓稿嚭绔暩(sh霉)閲�:750 I/O
    闆绘簮闆诲-鏈€灏�:850 mV
    闆绘簮闆诲-鏈€澶�:850 mV
    鏈€灏忓伐浣滄韩搴�:- 40 C
    鏈€澶у伐浣滄韩搴�:+ 100 C
    鏁�(sh霉)鎿�(j霉)閫熺巼:30.5 Gb/s
    瀹夎棰�(f膿ng)鏍�:SMD/SMT
    灏佽 / 绠遍珨:FBGA-1760
    鍟嗘(bi膩o):Xilinx
    鍒嗗竷寮廟AM:9.7 Mbit
    鍏�(n猫i)宓屽紡濉奟AM - EBR:88.6 Mbit
    婵曞害鏁忔劅鎬�:Yes
    閭忚集鏁�(sh霉)绲勫鏁�(sh霉)閲忊€斺€擫AB:89520 LAB
    宸ヤ綔闆绘簮闆诲:850 mV

鐗瑰緛

    铏曠悊绯荤当(t菕ng)
    UltraScale+ MPSoC 鍦嶇篂鍔熻兘璞愬瘜鐨勫洓鏍� ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5 铏曠悊绯荤当(t菕ng) (PS) 妲�(g貌u)寤恒€� 闄や簡 32 浣�/64 浣嶆噳(y墨ng)鐢ㄨ檿鐞嗗柈鍏� (APU) 鍜� 32 浣嶅鏅傝檿鐞嗗柈鍏� (RPU) 涔嬪锛孭S 閭勫寘鍚皥鐢ㄧ殑 ARM Mali-400 MP2 鍦栧舰铏曠悊鍠厓 (GPU)銆�
    I/O銆佹敹鐧�(f膩)鍣ㄣ€丳CIe銆�100G 浠ュお缍�(w菐ng)鍜� 150G Interlaken
    鏅傞悩鍜屽収(n猫i)瀛樻帴鍙�
    閰嶇疆銆佸姞瀵嗗拰绯荤当(t菕ng)鐩�(ji膩n)鎺�
    閬风Щ瑷�(sh猫)鍌�