鏅傞枔锛�2025/5/10 14:40:03
闁辫畝锛�26
XCKU085-2FLVB1760E 鏄竴娆剧敱 Xilinx锛堣辰闈堟�濓級鐢熺敘(ch菐n)鐨� Kintex UltraScale 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�銆傝┎绯诲垪鍣ㄤ欢閲囩敤 20nm 宸ヨ棟鎶�琛撳埗閫�锛屽皥鐐洪珮鎬ц兘銆佷綆鍔熻�楃殑鎳夌敤鍫存櫙瑷▓銆俋CKU085 鎻愪緵璞愬瘜鐨勯倧杓硣婧�銆丏SP 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬閫氫俊銆佷俊铏熻檿鐞嗐�佸湒鍍忚檿鐞�銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熺瓑闋樺煙銆�
銆�銆�姝ゅ瀷铏熺殑 FPGA 閰嶅倷浜嗗ぇ瀹归噺鐨勯倧杓柈鍏冨拰瀛樺劜鍣ㄨ硣婧�锛屽悓鏅傛敮鎸佸绋帴鍙ｅ崝(xi茅)璀板拰澶栭儴鍏�(n猫i)瀛樻帶鍒跺櫒锛屼娇鍏舵垚鐐洪渶瑕侀珮鏁�(sh霉)鎿�(j霉)鍚炲悙閲忓拰寰╅洔瑷堢畻浠诲嫏鐨勭悊鎯抽伕鎿�銆傛澶�锛孶ltraScale 鏋舵閭勬彁渚涗簡鍎�(y艒u)鍖栫殑鏅傞悩缍�(w菐ng)绲″拰淇¤櫉瀹屾暣鎬�锛岀⒑淇濆湪楂橀牷閬嬭涓嬬殑绌�(w臎n)瀹氭�ц兘銆�
鍨嬭櫉锛歑CKU085-2FLVB1760E
銆�銆�宸ヨ棟鍒剁▼锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 84,420 鍊� CLB 灏�
銆�銆�DSP 妯″鏁�(sh霉)閲忥細3,996 鍊�
銆�銆�鍏�(n猫i)缃� RAM 瀹归噺锛氱磩 5,300KB
銆�銆�閰嶇疆妯″紡锛氬柈寮曞皫锛圫ingle Boot锛夈�佸寮曞皫锛圡ulti Boot锛�
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 840 鍊嬬敤鎴跺彲鐢� I/O
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽褰㈠紡锛欶LVB1760锛�1760 寮曡叧 Fine Line Ball Grid Array锛�
XCKU085-2FLVB1760E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 瓒呭ぇ瑕�(gu墨)妯￠倧杓硣婧�锛岄仼鍚堝京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰绠楁硶瀵︾従(xi脿n)銆�
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄�熺巼鍙仈 16.3 Gbps锛屾敮鎸� PCIe Gen3銆丆PRI 鍜� JESD204B 绛夊崝(xi茅)璀�銆�
銆�銆�3. 鍏�(n猫i)缃� Block RAM 鍜屽垎甯冨紡 RAM锛屾豢瓒虫暩(sh霉)鎿�(j霉)绶╁瓨闇�姹傘��
銆�銆�4. DSP Slice 鏀寔楂樻晥鐨勬诞榛為亱绠楀拰婵炬尝鍣ㄨō瑷�銆�
銆�銆�5. 鍙厤缃殑鏅傞悩绠＄悊妯″锛屾彁渚涢潏娲荤殑鏅傞悩鍒嗛牷銆佸�嶉牷鍜岀浉绉诲姛鑳�銆�
銆�銆�6. 鏀寔 DDR4銆丏DR3 鍜� LPDDR3 鍏�(n猫i)瀛樻帴鍙�锛岄仼鎳変笉鍚岄鍨嬬殑澶栭儴瀛樺劜鍣ㄩ�ｆ帴銆�
銆�銆�7. 鍏�(n猫i)閮ㄩ浕婧愮鐞嗘鍒堕檷浣庢暣楂斿姛鑰�锛屽苟鍎�(y艒u)鍖栨暎鐔辨�ц兘銆�
銆�銆�8. 鍏堥�茬殑瀹夊叏鍔熻兘锛屽 AES 鍔犲瘑銆丼HA 鍫辨枃鎽樿鍜屼綅娴佽獚璀�锛屼繚璀风煡璀樼敘(ch菐n)娆婂拰绯荤当(t菕ng)瀹夊叏銆�
銆�銆�9. 鎻愪緵寮峰ぇ鐨勯枊鐧�(f膩)宸ュ叿 Vivado锛屽公鍔╃敤鎴跺揩閫熷畬鎴愯ō瑷�銆佷豢鐪熷拰椹楄瓑娴佺▼銆�
XCKU085-2FLVB1760E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛屽鐒＄窔鍩虹珯銆佸洖鍌崇恫(w菐ng)闂滃拰璺敱鍣ㄣ��
銆�銆�2. 瑕栭牷鍜屽湒鍍忚檿鐞�锛屽寘鎷珮娓呰闋荤法纰艰В纰�銆佽▓绠楁瑕栬鍜岄啱(y墨)鐧傛垚鍍�銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂紝渚嬪鎼滅储寮曟搸銆佹暩(sh霉)鎿�(j霉)搴鐞嗗拰澶ф暩(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒�锛屾兜钃嬫鍣ㄤ汉銆侀亱鍕曟帶鍒跺拰瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃�锛岀敤浜庨浄閬斾俊铏熻檿鐞�銆佸皫鑸郴绲�(t菕ng)鍜屽姞瀵嗛�氫俊銆�
銆�銆�6. 娓│娓噺瑷倷锛屽绀烘尝鍣�銆佷俊铏熺櫦(f膩)鐢熷櫒鍜屽崝(xi茅)璀板垎鏋愬剙銆�
銆�銆�7. 閱�(y墨)鐧傝ō鍌欙紝鍖呮嫭瓒呰伈娉㈠剙鍣�銆丆T 鎺冩弿鍎�鍜屽叾浠栭珮绮惧害瑷烘柗瑁濈疆銆�
XCKU060-2FFVA1156E
銆�銆�XCKU040-2FFVB1156E
銆�銆�XCKU085-3FLVB1760E
