XC7V690T-2FFG1761I 鏅�(sh铆)闁擄細2025/5/8 18:20:35 闁辫畝锛�31

XC7V690T-2FFG1761I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� 7 绯诲垪 Virtex-7 FPGA 鑺墖涔嬩竴锛屽爆浜庨珮绔� FPGA 绯诲垪銆傝┎鍣ㄤ欢閲囩敤鑷�(t谩i)绌嶉浕锛圱SMC锛夌殑 28nm 宸ヨ棟鍒堕€�锛屾彁渚涢珮閭忚集瀵嗗害銆佽睈瀵岀殑 DSP 妯″銆佸ぇ瀹归噺 Block RAM 鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ姛鑳�銆傚畠閬╃敤浜庨珮鎬ц兘瑷�(j矛)绠�銆佷俊铏�(h脿o)铏曠悊銆佽闋诲湒鍍忚檿鐞�銆侀€氫俊鍩虹(ch菙)瑷�(sh猫)鏂藉拰閱�(y墨)鐧傛垚鍍忕瓑寰�(f霉)闆滄噳(y墨ng)鐢ㄩ牁(l菒ng)鍩熴€�
銆€銆€姝ゅ瀷铏�(h脿o)涓殑 XC 琛ㄧず Xilinx 鍟嗙敤鐢�(ch菐n)鍝佺郴鍒�锛�7V 琛ㄧず Virtex-7 绯诲垪锛�690T 琛ㄧず鍏烽珨 FPGA 鍣ㄤ欢瑕�(gu墨)妯★紙绱勫寘鍚� 690K 閭忚集鍠厓锛�锛�-2 琛ㄧず閫熷害绛夌礆(j铆)锛孎(xi脿n)FG1761 琛ㄧず灏佽椤炲瀷鐐� 1761 寮曡叧鐨� F 绯诲垪灏佽锛屾渶鍚庣殑 I 琛ㄧず宸ヤ綔婧害鑼冨湇鐐哄伐妤�(y猫)绱�(j铆)锛�-40掳C 鑷� +100掳C锛�銆�

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閭忚集鍠厓锛�690K
銆€銆€閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�
銆€銆€RAM 瀹归噺锛�36.1Mb (Block RAM)
銆€銆€DSP 妯″锛�2,160鍊�(g猫)
銆€銆€涓茶鏀剁櫦(f膩)鍣ㄩ€熺巼锛氭渶楂� 13.1 Gbps
銆€銆€I/O 鏁�(sh霉)閲忥細1,092
銆€銆€宸ヤ綔闆诲锛�0.9V 鏍稿績闆诲锛�1.0V AUX 闆诲锛�1.8V 鎴� 3.3V I/O 闆诲
銆€銆€灏佽椤炲瀷锛欶FG1761 (1761 寮曡叧)
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C (宸ユキ(y猫)绱�(j铆))
銆€銆€宸ヨ棟绡€(ji茅)榛�(di菐n)锛�28nm
銆€銆€鍔熻€楋細鍙栨焙浜庝娇鐢ㄥ牬(ch菐ng)鏅�锛屽吀鍨嬪嫊(d貌ng)鎱�(t脿i)鍔熻€� < 10W

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