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XC7A75T-2CSG324C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖銆侫rtix-7 绯诲垪鏄熀浜� 28nm 宸ヨ棟鍒堕�犵殑楂樻�ц兘銆佷綆鍔熻�楃従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 (FPGA)锛岄仼鐢ㄤ簬閫氫俊銆佹秷璨婚浕瀛�銆佸伐妤�(y猫)鑷嫊鍖栦互鍙婇啱(y墨)鐧傛垚鍍忕瓑闋�(l菒ng)鍩熺殑寰╅洔淇¤櫉铏曠悊鍜屽祵鍏ュ紡瑷堢畻浠诲嫏銆�
銆�銆�瑭插瀷铏熷叿鏈夎睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣紝鏀寔闈堟椿鐨勭郴绲�(t菕ng)闆嗘垚鍜岃ō瑷堝劒(y艒u)鍖�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛欰rtix-7
銆�銆�灏佽锛欳SG (Flip-Chip BGA)
銆�銆�寮曡叧鏁�(sh霉)锛�324
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細75K
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel, etc.
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O 閵�琛岄浕澹擄細1.8V / 2.5V / 3.3V
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�瀛樺劜鍣ㄨ硣婧愶細绱� 2.9 Mb (BRAM)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細180
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銆�銆�2. 闆嗘垚浜� 180 鍊� DSP Slice锛屽皥闁�鐢ㄤ簬楂樻晥鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欙紝渚嬪婵炬尝銆丗FT 鍜岀煩闄ｉ亱绠�銆�
銆�銆�3. 鏀寔楂橀仈 6.5 Gbps 鐨� GTX 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬 PCIe Gen2銆佸崈鍏嗕互澶恫(w菐ng)鍜屽厜绾栭�氶亾绛夋帴鍙�銆�
銆�銆�4. 鍏�(n猫i)缃ぇ瀹归噺 Block RAM 鍜屽垎甯冨紡 RAM锛岀偤鏁�(sh霉)鎿�(j霉)绶╁瓨鍜� FIFO 鎻愪緵瓒冲鐨勫瓨鍎茬┖闁�銆�
銆�銆�5. 鎻愪緵澶氱ó閰嶇疆閬搁爡锛屽寘鎷� Slave Serial銆丮aster Parallel 绛�锛岀⒑淇濋潏娲绘�у拰鏄撶敤鎬с��
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銆�銆�7. 绗﹀悎 RoHS 妯欐簴锛岄噰鐢ㄧ劇閴涘皝瑁�锛岄仼鍚堢挵(hu谩n)淇濊姹傞珮鐨勬噳鐢ㄧ挵(hu谩n)澧�銆�
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銆�銆�3. 鐒＄窔閫氫俊鍩虹(ch菙)瑷柦锛屼緥濡傚熀绔欎腑鐨勪俊铏熻(di脿o)鍒惰В瑾�(di脿o)鍜屽崝(xi茅)璀拌檿鐞�銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欎腑鐨勮秴鑱叉尝鎴愬儚銆丆T 鎺冩弿鏁�(sh霉)鎿�(j霉)铏曠悊銆�
銆�銆�5. 楂樻�ц兘瑷堢畻骞宠嚭锛岀敤浜庣瀛歌▓绠楁垨浜哄伐鏅鸿兘鎺ㄧ悊鍔犻��銆�
銆�銆�6. 鏁�(sh霉)鎿�(j霉)涓績缍�(w菐ng)绲′氦鎻涙鍜岃矾鐢卞櫒涓殑娴侀噺绠＄悊鑸囧寘铏曠悊鍔熻兘瀵︾従(xi脿n)銆�
XC7A75T-2FTG256C
銆�銆�XC7A75T-2FGG484C
銆�銆�XC7A75T-2FBG484C
