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XC7A50T-2CS325I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖锛屽爆浜� 7 绯诲垪楂樼 FPGA 涓殑浣庡姛鑰楃敘(ch菐n)鍝佺窔銆傝┎鍣ㄤ欢閲囩敤 28nm 宸ヨ棟鍒堕€�锛屽叿鏈夐珮鎬ц兘銆佷綆鍔熻€楀拰璞愬瘜鐨勯倧杓硣婧�锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佽埅绌鸿埅澶╁強鍦嬮槻绛夐牁(l菒ng)鍩�銆侫rtix-7 绯诲垪 FPGA 闈㈠悜涓鎳�(y墨ng)鐢�锛屾彁渚涗簡鍎�(y艒u)绉€鐨勬€у児姣斿拰闈堟椿鎬�銆�
銆€銆€XC7A50T-2CS325I 鎻愪緵浜� 50,640 鍊嬮倧杓柈鍏冿紙Logic Cells锛夛紝骞堕泦鎴愪簡 Block RAM銆丏SP Slice 鍜岄珮閫熸敹鐧�(f膩)鍣ㄧ瓑璩囨簮锛屾敮鎸佸绋帴鍙ｅ崝(xi茅)璀板拰寰�(f霉)闆滅畻娉曞(sh铆)鐝�(xi脿n)銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑C7A50T-2CS325I
銆€銆€鍝佺墝锛歑ilinx
銆€銆€绯诲垪锛欰rtix-7
銆€銆€宸ヨ棟锛�28nm
銆€銆€閭忚集鍠厓锛�50,640
銆€銆€RAM 璩囨簮锛氱磩 2.9 Mb (Distributed RAM + Block RAM)
銆€銆€DSP Slice 鏁�(sh霉)閲忥細120
銆€銆€I/O 鏁�(sh霉)閲忥細325
銆€銆€閰嶇疆妯″紡锛歋lave Serial
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€灏佽褰㈠紡锛欳SBGA (19x19 mm)
銆€銆€閫熷害绛夌礆锛�-2

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XC7A50T-2CS325I 鐨勪富瑕佺壒鎬у寘鎷細
銆€銆€1. 楂樻€ц兘鑸囦綆鍔熻€楋細閲囩敤 28nm HPT 宸ヨ棟鎶€琛�(sh霉)锛屽湪淇濊瓑楂樻€ц兘鐨勫悓鏅傚ぇ骞呴檷浣庨潨鎱�(t脿i)鍔熻€�銆�
銆€銆€2. 闈堟椿鐨勯倧杓硣婧愶細鎻愪緵瓒呴亷 50K 鐨勯倧杓柈鍏�锛岃兘澶犳豢瓒冲京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗛渶姹傘€�
銆€銆€3. 鍏�(n猫i)宓屽瓨鍎茶硣婧愶細闆嗘垚澶у閲忕殑 Block RAM 鍜� Distributed RAM锛屽彲闈堟椿閰嶇疆鐐� FIFO銆侀洐绔彛 RAM 鎴� Lookup Table銆�
銆€銆€4. DSP 鏀寔锛氭瘡鍊� DSP Slice 鎻愪緵 27x18 浣嶄箻娉曞櫒鍜� 48 浣嶇疮鍔犲櫒锛岄仼鍚堥珮鎬ц兘瑷堢畻浠诲嫏(w霉)銆�
銆€銆€5. 澶氭ǎ鍖栫殑 I/O 鏀寔锛氭敮鎸佸绋(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe銆丟igabit Ethernet 鍜� USB銆�
銆€銆€6. 鍙摯(ku貌)灞曟€э細鏀寔鑸囧叾浠� Artix-7 绯诲垪鎴栨洿楂樼鐨� Kintex/Virtex 绯诲垪 FPGA 閫�(j矛n)琛岀劇绺崝(xi茅)浣溿€�
銆€銆€7. 鍏�(n猫i)缃檪閻樼鐞嗘ā濉婏細闆嗘垚 PLL 鍜� MMCM锛屾敮鎸侀潏娲荤殑鏅傞悩鍒嗛厤鍜岄牷鐜囧悎鎴�銆�
銆€銆€8. 閰嶇疆鏂瑰紡澶氭ǎ锛氭敮鎸� Slave Serial銆丮aster SPI 鍜� JTAG 绛夊绋厤缃ā寮�銆�

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XC7A50T-2CS325I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇绶氬熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞�銆�
銆€銆€2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瀵�(sh铆)鏅傝闋荤法纰�/瑙ｇ⒓銆佸湒鍍忓寮�(qi谩ng)鍜岃▓绠楁(j墨)瑕栬銆�
銆€銆€3. 宸ユキ(y猫)鑷嫊鍖栵細瀵�(sh铆)鐝�(xi脿n)閬�(y霉n)鍕曟帶鍒�銆佹(j墨)鍣ㄤ汉绯荤当(t菕ng)鍜屽伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)銆�
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銆€銆€7. 娓│鑸囨脯閲忥細鐢ㄤ簬绀烘尝鍣�銆佷俊铏熺櫦(f膩)鐢熷櫒鍜屽叾浠栫簿瀵嗘脯瑭﹁ō(sh猫)鍌�銆�