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鍨嬭櫉锛歑C7A35T-2CSG324I
銆�銆�FPGA绯诲垪锛欰rtix-7
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細35K
銆�銆�RAM瀹归噺锛�1.4Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細90鍊�
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master SPI
銆�銆�I/O寮曡叧鏁�(sh霉)閲忥細226
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽褰㈠紡锛欳SG324
銆�銆�鏅傞悩绠＄悊璩囨簮锛�1鍊婱MCM锛�1鍊婸LL
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹撶偤0.9V锛岃紨鍔╅浕澹撶偤1.8V鎴�3.3V
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銆�銆�姝ゅ锛孹C7A35T-2CSG324I 閭勯泦鎴愪簡 Xilinx Vivado 瑷▓濂椾欢鏀寔锛屽厑瑷卞伐绋嬪斧蹇�熼枊鐧�(f膩)鍜岄璀夎ō瑷堛��
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XC7A50T-2CSG324I
銆�銆�XC7A100T-2CSG324I
