鏅傞枔锛�2025/5/8 11:32:20
闁辫畝锛�29
XC6VLX365T-L1FFG1156I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-6 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�俈irtex-6 绯诲垪鏄熀浜� 40nm 宸ヨ棟鍒堕�犵殑楂樻�ц兘 FPGA锛屽唬娉涙噳鐢ㄤ簬閫氫俊銆佽埅绌鸿埅澶┿�佸唬鎾拰宸ユキ(y猫)闋樺煙銆�
銆�銆�Virtex-6 FPGA 鎻愪緵浜嗗挤澶х殑閭忚集璩囨簮銆佸祵鍏ュ紡瀛樺劜鍣�銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄤ互鍙� DSP Slice 绛夊姛鑳芥ā濉�銆傝┎鑺墖鏀寔澶氱ó鎺ュ彛鍗�(xi茅)璀�锛屽苟鍏锋湁楂樺付瀵拰浣庡欢閬茬殑鐗归粸锛岄仼鍚堝京闆滅殑瑷▓闇�姹�銆�
绯诲垪锛歏irtex-6
銆�銆�鍨嬭櫉锛歑C6VLX365T-L1FFG1156I
銆�銆�宸ヨ棟锛�40nm
銆�銆�閭忚集鍠厓鏁搁噺锛氱磩 365,000
銆�銆�DSP Slice 鏁搁噺锛�2,160
銆�銆�Block RAM 瀹归噺锛氱磩 20.7 Mb
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚澶栭儴閰嶇疆闁冨瓨
銆�銆�I/O 寮曡叧鏁革細840
銆�銆�灏佽椤炲瀷锛欶FG1156
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� +85掳C锛�
銆�銆�閫熷害绛夌礆锛歀1
XC6VLX365T-L1FFG1156I 鎻愪緵璞愬瘜鐨勭壒鎬т互婊胯冻楂樻�ц兘瑷堢畻鍜屼俊铏熻檿鐞嗙殑闇�姹�銆�
銆�銆�1. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈 6.5 Gbps 鐨勬暩鎿氬偝杓搁�熺巼锛岄仼鐢ㄤ簬鍚勭ó閫氫俊鍗�(xi茅)璀板 PCIe銆丼ATA 鍜� Gigabit Ethernet銆�
銆�銆�2. 宓屽叆寮忓瓨鍎插櫒锛氬収缃ぇ閲� Block RAM 鍜屽垎甯冨紡 RAM锛岃兘澶犳湁鏁堟敮鎸佹暩鎿氱珐瀛樺拰 FIFO 鎳夌敤銆�
銆�銆�3. DSP Slice锛氭瘡鍊� DSP Slice 鍖呭惈灏堢敤涔樻硶鍣ㄥ拰鍔犳硶鍣�锛屾サ澶у湴鎻愬崌浜嗘暩瀛椾俊铏熻檿鐞嗚兘鍔涖��
銆�銆�4. I/O 鍙法绋嬫�э細闈堟椿鐨� I/O 妯欐簴鍏煎鎬�锛屽厑瑷辩敤鎴舵牴鎿氬叿楂旀噳鐢ㄩ伕鎿囦笉鍚岀殑闆诲钩妯欐簴銆�
銆�銆�5. 鍏ч儴鏅傞悩绠＄悊锛氭彁渚� PLL 鍜� DCM 妯″锛岀敤浜庣敓鎴愬拰鍒嗛牷绯荤当(t菕ng)鏅傞悩銆�
銆�銆�6. 宓屽叆寮忕‖鏍� IP锛氬寘鎷崈鍏嗕互澶恫 MAC銆丳CI Express 绛夌‖鏍告ā濉�锛岀啊鍖栦簡寰╅洔鍗�(xi茅)璀扮殑瀵︾従閬庣▼銆�
銆�銆�7. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤 ASMBL 鏋舵鍒嗗壊 FPGA 鐐哄鍊嬪崁(q奴)鍩燂紝寰炶�岄檷浣庢暣楂斿姛鑰楀苟鎻愰珮鏁ｇ啽鏁堢巼銆�
瑭茶姱鐗囬仼鐢ㄤ簬澶氱ó楂樼鎳夌敤鍫存櫙锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁告摎鍖呰檿鐞嗚垏杞夌櫦(f膩)銆�
銆�銆�2. 瑕栭牷铏曠悊锛氬唬鎾ō鍌欎腑鐨勮闋荤法纰笺�佽В纰煎強鍦栧儚澧炲挤銆�
銆�銆�3. 娓│娓噺锛氬鏅傛暩鎿氶噰闆嗗拰鍒嗘瀽鍎�鍣ㄣ��
銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈠拰鍏朵粬閱�(y墨)瀛告垚鍍忕郴绲�(t菕ng)鐨勪俊铏熻檿鐞�銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈淇¤櫉铏曠悊銆佽(w猫i)鏄熼�氫俊绛変换鍕�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細閬嬪嫊鎺у埗鍜屾鍣ㄨ瑕虹郴绲�(t菕ng)涓殑鏁告摎铏曠悊鑸囨焙绛�銆�
XC6VLX365T-1FFG1156C
銆�銆�XC6VLX365T-1FFG1156I
銆�銆�XC6VLX365T-2FFG1156C
銆�銆�XC6VLX365T-2FFG1156I
