XC5VLX20T-1FFG323I 鏅�(sh铆)闁擄細2022/10/20 14:04:59 闁辫畝锛�640

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC5VLX20T-1FFG323I
鎻忚堪	IC FPGA 172 I / O 323FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC5VLX20T-1FFG323I
鎻忚堪	IC FPGA 172 I / O 323FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Virtex?-5 LXT
閮ㄥ垎鐙€鎱�(t脿i)	娲绘€�
鍖�/绠�	323-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	323-FCBGA(19x19)
鍩虹(ch菙)閮ㄤ欢铏�(h脿o)	XC5VLX20T

鐗规€�

Virtex-5 LXT锛氬叿鏈夐珮绱�(j铆)涓茶閫ｆ帴鐨勯珮鎬ц兘閭忚集

LXT鍣ㄤ欢閲囩敤鍙(di脿o)闆诲瑾�(di脿o)绡€(ji茅)鍣�锛屽湪鍚屼竴灏佽涓吋瀹�

鏈€鍏堥€�(j矛n)锛岄珮鎬ц兘锛屾渶浣冲埄鐢ㄧ巼鐨凢PGA鏋舵(g貌u)

鐪熸鐨�6杓稿叆鏌ユ壘琛�(LUT)鎶€琛�(sh霉)

闆�5-LUT閬搁爡(xi脿ng)

鏀归€�(j矛n)鐨勬笡灏戣烦韬嶈矾鐢�

64浣嶅垎甯冨紡RAM閬搁爡(xi脿ng)

SRL32 / Dual SRL16閬搁爡(xi脿ng)

寮�(qi谩ng)澶х殑鏅�(sh铆)閻樼鐞嗙璨�(CMT)鏅�(sh铆)閻�

鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)闃绘闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅�(sh铆)閻樼浉绉�

PLL妯″鐢ㄤ簬杓稿叆鎶栧嫊(d貌ng)婵炬尝锛岄浂寤堕伈绶╂矕锛岄牷鐜囧悎鎴愬拰鐩镐綅鍖归厤鏅�(sh铆)閻樺垎闋�

36-Kbit Block RAM / FIFO

鐪熸鐨勯洐绔彛RAM妯″

澧炲挤(qi谩ng)鐨勫彲閬稿彲绶ㄧ▼FIFO閭忚集

鍙法绋� - 鐪熸鐨勯洐绔彛瀵害鍙仈(d谩)x36 - 绨�(ji菐n)鍠殑闆欑鍙ｅ搴﹀彲閬�(d谩)x72

鍏�(n猫i)缃彲閬哥殑绯鹃尟(cu貌)闆昏矾

鍙伕鎿囧皣姣忓€�(g猫)濉婄法绋嬬偤鍏╁€�(g猫)鐛�(d煤)绔嬬殑18-Kbit濉�

楂樻€ц兘骞惰SelectIO鎶€琛�(sh霉)

1.2鑷�3.3VI / O鎿嶄綔

浣跨敤ChipSync鎶€琛�(sh霉)閫�(j矛n)琛屾簮鍚屾鎺ュ彛

鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜

闈堟椿鐨勭窗(x矛)绮掑害I / O閵€琛屾キ(y猫)鍕�(w霉)

楂橀€熷収(n猫i)瀛樻帴鍙ｆ敮鎸�

鍏堥€�(j矛n)鐨凞SP48E鍒囩墖

25 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屼箻娉�

鍙伕鐨勫姞娉曞櫒锛屾笡娉曞櫒鍜岀疮鍔犲櫒

鍙伕鐨勬祦姘寸窔

鍙伕鐨勬寜浣嶉倧杓姛鑳�

灏堢敤绱�(j铆)鑱�(li谩n)閫ｆ帴

闈堟椿鐨勯厤缃伕闋�(xi脿ng)

SPI鍜屽苟琛孎LASH鎺ュ彛

鍏锋湁灏堢敤鍥為€€閲嶉厤缃倧杓殑澶氭瘮鐗规祦鏀寔

鑷嫊(d貌ng)绺界窔瀵害妾㈡脯(c猫)鍔熻兘

鎵€鏈夎ō(sh猫)鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)鎺у姛鑳�

鐗囦笂/鐗囧鐔辩洠(ji膩n)鎺�

鐗囦笂/鐗囧闆绘簮鐩�(ji膩n)鎺�

JTAG瑷晱鎵€鏈夊彈鐩�(ji膩n)鎺х殑鏁�(sh霉)閲�

鐢ㄤ簬PCI Express瑷�(sh猫)瑷�(j矛)鐨勯泦鎴愮榛�(di菐n)妯″

涓夋ā10/100/1000 Mb / s浠ュお缍�(w菐ng)MAC

RocketIO GTP鏀剁櫦(f膩)鍣�100 Mb / s鑷�3.75 Gb / s

LXT鍜孲XT骞宠嚭(t谩i)

65绱嶇背閵匔MOS宸ヨ棟鎶€琛�(sh霉)

1.0V鏍稿績闆诲

楂樹俊铏�(h脿o)瀹屾暣鎬у€掕鑺墖灏佽锛屾彁渚涙(bi膩o)婧�(zh菙n)鎴栫劇閴涘皝瑁濋伕闋�(xi脿ng)

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
绺絉AM浣嶆暩(sh霉)	958464
瀹夎椤炲瀷	琛ㄩ潰璨艰
宸ヤ綔婧害	-40掳C~100掳C(TJ)
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅�(sh铆)閻橀牷鐜�-鏈€澶у€�	1098.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B323
JESD-609浠ｇ⒓	E1
CLB鏁�(sh霉)閲�	1560.0
杓稿叆鏁�(sh霉)閲�	172.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	19968.0
杓稿嚭鏁�(sh霉)閲�	172.0
绲傜鏁�(sh霉)閲�	323
绲勭箶	1560 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	250
闆绘簮	1,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.85姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲	1.0 V
闆绘簮闆诲-鏈€灏忓€�	0.95 V
闆绘簮闆诲-鏈€澶у€�	1.05 V
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	涓夊崄
闀�(zh菐ng)搴�	19.0姣背
瀵害	19.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍�(ji脿)浠ｇ⒓	BGA323,18X18,40
鍖呰褰㈢媭	寤ｅ牬(ch菐ng)
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	19 X 19 MM锛岀劇閴�锛孎(xi脿n)BGA-323