鏅傞枔锛�2025/5/10 17:27:46
闁辫畝锛�22
XC5VLX110-2FFG1760I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-5绯诲垪FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍊嬪瀷铏�銆傝┎绯诲垪FPGA閲囩敤鍏堥�茬殑65nm宸ヨ棟鍒堕�狅紝鍏锋湁楂橀倧杓瘑搴�銆侀珮鎬ц兘鍜屼綆鍔熻�楃殑鐗归粸锛屽唬娉涙噳鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鑷嫊鍖�銆侀啱(y墨)鐧傝ō鍌欍�佽埅绌鸿埅澶╃瓑闋樺煙銆�
銆�銆�Virtex-5 FPGA鍒嗙偤澶氬�嬪瓙绯诲垪锛屽寘鎷琇X锛堥倧杓劒(y艒u)鍖栵級銆丗X锛堝祵鍏ュ紡铏曠悊鍎�(y艒u)鍖栵級銆丼X锛圖SP鍎�(y艒u)鍖栵級绛夛紝鑰孹C5VLX110灞簬LX瀛愮郴鍒�锛屼富瑕侀嚌灏嶉珮閭忚集闇�姹傜殑鎳夌敤鍫存櫙銆�
鍨嬭櫉锛歑C5VLX110-2FFG1760I
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩110,000鍊�
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃杻瀛�锛岄渶澶栭儴閰嶇疆瀛樺劜鍣�
銆�銆�I/O寮曡叧鏁�(sh霉)锛氭渶澶�940鍊�
銆�銆�灏佽椤炲瀷锛欶FG1760
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C鑷�85掳C锛�
銆�銆�宸ヨ棟绡�(ji茅)榛烇細65nm
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹�1.0V锛孖/O闆诲1.8V/2.5V/3.3V
XC5VLX110-2FFG1760I鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氭敮鎸侀珮閬�500 MHz鐨勬檪閻橀牷鐜�锛岄仼鍚堥渶瑕侀珮閫熸暩(sh霉)鎿�(j霉)铏曠悊鐨勬噳鐢ㄣ��
銆�銆�2. 宓屽叆寮忓瓨鍎插櫒濉婏細鎻愪緵澶у閲廈lock RAM鍜屽垎甯冨紡RAM璩囨簮锛岀敤浜庢暩(sh霉)鎿�(j霉)绶╁瓨鍜岃嚚鏅傚瓨鍎�銆�
銆�銆�3. DSP Slice锛氶泦鎴愬皥鐢ㄧ殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗘ā濉�锛岃兘澶犻珮鏁堝鐝�(xi脿n)涔樻硶绱姞閬嬬畻銆�
銆�銆�4. 鏀寔澶氱ó鎺ュ彛妯欐簴锛氬寘鎷琍CI Express銆佸崈鍏嗕互澶恫(w菐ng)銆丷ocketIO涓茶鏀剁櫦(f膩)鍣ㄧ瓑锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勫京闆滈渶姹�銆�
銆�銆�5. 鍔熻�楃鐞嗭細閫氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鍜屾檪閻橀杸鎺ф妧琛撻檷浣庢暣楂斿姛鑰椼��
銆�銆�6. 鍙摯灞曟�у挤锛氭敮鎸佽垏鍏朵粬Virtex-5 FPGA鐒＄斧閫ｆ帴锛屾寤烘洿澶ц(gu墨)妯＄殑绯荤当(t菕ng)銆�
XC5VLX110-2FFG1760I閬╃敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛�銆�
銆�銆�2. 宸ユキ(y猫)鎺у埗锛氫緥濡傚鏅傛暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗙郴绲�(t菕ng)銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬CT鎺冩弿鍎�銆佽秴鑱叉尝瑷倷涓殑鍦栧儚铏曠悊銆�
銆�銆�4. 娓│娓噺锛氬鐝�(xi脿n)寰╅洔鐨勬脯瑭﹀剙鍣ㄥ姛鑳�銆�
銆�銆�5. 杌嶄簨鑸囪埅澶╋細鍦ㄨ姹傞珮鍙潬鎬у拰瑷堢畻鑳藉姏鐨勭挵(hu谩n)澧冧腑浣跨敤銆�
銆�銆�6. 瑕栭牷铏曠悊锛氭敮鎸侀珮娓呰闋绘祦鐨勭法纰艰В纰煎強鍦栧儚澧炲挤銆�
XC5VLX110T-2FFG1760I
銆�銆�XC5VLX110T-3FFG1760I
銆�銆�XC5VLX110-3FFG1760I
