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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC4VLX25-10SF363I

XC4VLX25-10SF363I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2022/10/26 10:32:31 鏌ョ湅 闁辫畝锛�964

鐢�(ch菐n)鍝佸瀷铏�

XC4VLX25-10SF363I

鎻忚堪

闆嗘垚闆昏矾FPGA 240 I / O 363FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�

XC4VLX25-10SF363I

鎻忚堪

闆嗘垚闆昏矾FPGA 240 I / O 363FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-4LX

鎵撳寘

鎵樼洡

闆朵欢鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

1.14V1.26V

宸ヤ綔婧害

-40掳C100掳C(TJ)

鍖呰/绠�

363-FBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

363-FCBGA(17x17)

鍩烘湰闆朵欢铏�

XC4VLX25

鐗规��

    Virtex-4LX锛氶珮鎬ц兘閭忚集鎳�(y墨ng)鐢ㄨВ姹烘柟妗�

    Xesium鏅傞悩鎶�琛�(sh霉)

    鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)妯″

    闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)

    宸垎鍏ㄥ眬鏅傞悩

    XtremeDSP Slice

    18x18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屼箻鏁�(sh霉)

    鍙伕鐨勭閬撻殠娈�

    鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

    鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

    鍒嗗竷寮廟AM

    闆欑鍙�18KbitRAM濉娐峰彲閬哥殑绠＄窔绱毬峰彲閬哥殑鍙法绋婩IFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉

    楂橀�熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2SDRAM锛孮DR-II鍜孯LDRAM-II銆�

    SelectIO鎶�琛�(sh霉)

    1.5V鑷�3.3VI/O鎿嶄綔

    鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)

    鏁�(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜

    绱�(x矛)绮掑害鐨処/O閵�琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴鍊嬮妧琛屼腑閰嶇疆)

    闈堟椿鐨勯倧杓硣婧�

    瀹夊叏鑺墖AES浣嶆祦鍔犲瘑

    90nm閵匔MOS宸ヨ棟

    1.2V鏍稿績闆诲

    鍊掕鑺墖灏佽锛屽寘鎷劇閴涘皝瑁濋伕鎿�


鍙冩暩(sh霉)

鍒堕�犲晢鍖呰瑾槑

FBGA-363

绗﹀悎REACH

鏄�

鐙�鎱�(t脿i)

娲绘��

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

鏈�澶ф檪閻橀牷鐜�

1028.0鍏嗚但

JESD-30浠ｇ⒓

S-PBGA-B363

JESD-609浠ｇ⒓

00

绺絉AM浣�

1327104

CLB鏁�(sh霉)閲�

2688.0

杓稿叆鏁�(sh霉)閲�

240.0

閭忚集鍠厓鏁�(sh霉)

24192.0

杓稿嚭鏁�(sh霉)閲�

240.0

绔瓙鏁�(sh霉)

363

绲勭箶

2688 CLBS

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰浠ｇ⒓

FBGA

鍖呰绛夋晥浠ｇ⒓

BGA363,20X20,32

鍖呰褰㈢媭

鍥涙柟褰�

鍖呰褰㈠紡

缍�(w菐ng)鏍兼帓鍒�锛岀簿绱�(x矛)闁撹窛

宄板�煎洖娴佹韩搴�(鈩�)

225

搴ч珮

1.99姣背

瀛愰鍒�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

1.2浼�

鏈�灏忎緵闆婚浕澹�

1.14浼�

鏈�澶ч浕婧愰浕澹�

1.26浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

绲傜瀹屾垚

閷�/閴�(Sn63Pb37)

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

0.8姣背

绲傜浣嶇疆

搴曢儴

鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶�(绉�)

30

闀峰害

17.0姣背

瀵害

17.0姣背

xc4vlx25-10sf363i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc4vlx25-10sf363i鐢�(ch菐n)鍝�

xc4vlx25-10sf363i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰90
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-4 LX
  • LAB/CLB鏁�(sh霉)2688
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)24192
  • RAM 浣嶇附瑷�(j矛)1327104
  • 杓稿叆/杓稿嚭鏁�(sh霉)240
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲1.14 V ~ 1.26 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨363-FBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�363-FCBGA锛�17x17锛�