鏅傞枔锛�2025/5/9 11:28:49
闁辫畝锛�24
XC4VLX15-11FF668C鏄疿ilinx鍏徃Virtex-4绯诲垪FPGA涓殑涓�鍝�锛屽爆浜庝綆鎴愭湰鐨凩X瀛愮郴鍒�銆傝┎鍣ㄤ欢閲囩敤鍏堥�茬殑90nm宸ヨ棟鍒堕�狅紝鎻愪緵寮峰ぇ鐨勯倧杓硣婧愬拰璞愬瘜鐨勫祵鍏ュ紡鍔熻兘妯″锛岄仼鐢ㄤ簬鍚勭ó楂樻�ц兘鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰寰╅洔鎺у埗閭忚集鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�XC4VLX15鍏峰倷15,260鍊嬮倧杓柈鍏冿紙Logic Cells锛�锛屾敮鎸佸绋厤缃伕闋�銆佹檪閻樼鐞嗕互鍙婂绋珮閫熶覆琛屾帴鍙�銆傚叾灏佽褰㈠紡鐐篎F668锛屽叿鏈夊ぇ閲廔/O寮曡叧锛岄仼鍚堥渶瑕侀珮瀵嗗害浜掗�ｇ殑瑷�(sh猫)瑷�銆�
鍨嬭櫉锛歑C4VLX15-11FF668C
銆�銆�绯诲垪锛歏irtex-4 LX
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細15,260
銆�銆�瀛樺劜鍣細576KB Block RAM
銆�銆�涔樻硶鍣細64鍊�18x18涔樻硶鍣�
銆�銆�DSP Slice锛氱劇
銆�銆�IOB鏁�(sh霉)閲忥細532
銆�銆�鏈�澶х敤鎴禝/O锛�420
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel, Boundary Scan
銆�銆�閫熷害绛夌礆锛�-11
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽锛欶F668
XC4VLX15-11FF668C鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氬熀浜嶺ilinx Virtex-4绯诲垪鐨勭当(t菕ng)涓�鏋舵(g貌u)瑷�(sh猫)瑷堬紝鍙鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺�銆�
銆�銆�2. 鍏�(n猫i)缃瓸lock RAM锛氭彁渚涢珮閬�576KB鐨勭墖涓婂瓨鍎茶硣婧愶紝鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕鎴栨煡鎵捐〃绛夊姛鑳�銆�
銆�銆�3. 宓屽叆寮忎箻娉曞櫒锛氬寘鍚�64鍊�18x18鐨勫皥鐢ㄧ‖浠朵箻娉曞櫒锛屽劒(y艒u)鍖栦簡DSP鎳夌敤涓殑涔樻硶閬嬬畻鏁堢巼銆�
銆�銆�4. 璞愬瘜鐨処/O鏀寔锛氬閬�420鍊嬬敤鎴跺彲鐢↖/O锛屽吋瀹瑰绋浕澹撴婧�锛屾豢瓒冲妯ｅ寲鐨勬帴鍙ｉ渶姹�銆�
銆�銆�5. 鏅傞悩绠＄悊锛氶泦鎴愭暩(sh霉)瀛楁檪閻樼鐞嗘ā濉婏紙DCM锛夛紝鏀寔鏅傞悩鍒嗛牷銆佸�嶉牷鍙婄浉浣嶈(di脿o)鏁寸瓑鍔熻兘銆�
銆�銆�6. 閰嶇疆闈堟椿锛氭敮鎸佸绋厤缃柟寮忥紝渚夸簬绯荤当(t菕ng)闆嗘垚鍜岃(di脿o)瑭�銆�
銆�銆�7. 宸ヨ棟鍏堥�诧細閲囩敤90nm宸ヨ棟鍒堕��锛屽姛鑰楄純浣庝笖鎬ц兘鍎�(y艒u)瓒娿��
XC4VLX15-11FF668C閬╃敤浜庡绋伐妤�(y猫)鍜屽晢妤�(y猫)闋�(l菒ng)鍩燂細
銆�銆�1. 鏁�(sh霉)瀛椾俊铏熻檿鐞嗭細濡傞煶闋�/瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忚檿鐞嗙瓑銆�
銆�銆�2. 閫氫俊瑷�(sh猫)鍌欙細濡傚熀甯惰檿鐞�銆佸崝(xi茅)璀拌綁(zhu菐n)鎻涚瓑銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鎺у埗鍜屾暩(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愶細濡傝秴鑱叉垚鍍�銆侀啱(y墨)鐧傜洠(ji膩n)娓ō(sh猫)鍌欑瓑銆�
銆�銆�5. 娓│鑸囨脯閲忥細鍦ㄦ脯瑭﹀剙鍣ㄤ腑瀵︾従(xi脿n)寰╅洔鐨勭畻娉曞拰淇¤櫉鐢熸垚銆�
銆�銆�6. 娑堣不椤為浕瀛愶細濡傞珮娓呴浕瑕栥�佹父鎴叉绛夌敘(ch菐n)鍝佷腑鐨勬牳蹇冮倧杓帶鍒堕儴鍒�銆�
XC4VLX15-10FF668C
銆�銆�XC4VLX15-12FF668C
