鏅傞枔锛�2023/7/7 14:31:31
闁辫畝锛�673
XC3SD1800A-5FGG676C鏄互Spartan-3AFPGA绯诲垪鐨勬垚鍔熺偤鍩虹锛屽鍔犱簡姣忓�嬮倧杓殑鍏�(n猫i)瀛橀噺骞舵坊鍔犱簡XtremeDSPDSP48Aslice銆傛柊鍔熻兘鎻愰珮浜嗙郴绲�(t菕ng)鎬ц兘骞堕檷浣庝簡閰嶇疆鎴愭湰銆傞�欎簺Spartan-3ADSPFPGA澧炲挤鍔熻兘鑸囩稉(j墨ng)閬庨璀夌殑90nm宸ヨ棟鎶�琛�(sh霉)鐩哥祼(ji茅)鍚�锛屾瘡缇庡厓鍙彁渚涙瘮浠ュ線鏇村鐨勫姛鑳藉拰甯跺锛岀偤鍙法绋嬮倧杓拰DSP铏曠悊琛屾キ(y猫)妯圭珛浜嗘柊妯欐簴銆�
鐢�(ch菐n)鍝佸瀷铏� | XC3SD1800A-5FGG676C |
鎻忚堪 | 闆嗘垚闆昏矾 FPGA 519 I/O 676FBGA |
椤炲垾 | 闆嗘垚闆昏矾 (IC)锛屽祵鍏ュ紡 - FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx Inc. |
绯诲垪 | Spartan?-3A DSP |
闆诲 - 闆绘簮 | 1.14V ~ 1.26V |
宸ヤ綔婧害 | 0掳C ~ 85掳C (TJ) |
鍖呰/绠� | 676-BGA |
渚涙噳鍟嗚ō鍌欏寘 | 676-FBGA (27x27) |
鍩烘湰闆朵欢铏� | XC3SD1800 |
XC3SD1800A-5FGG676C
鐢�(ch菐n)鍝佺ó椤� | FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鏅傞悩闋荤巼-鏈�澶� | 280.0 鍏嗚但 |
JESD-30 浠ｇ⒓ | S-PBGA-B676 |
JESD-609 浠ｇ⒓ | e1 |
CLB 鏁�(sh霉)閲� | 4160.0 |
绛夋晥闁�鏁�(sh霉) | 1800000.0 |
杓稿叆鏁�(sh霉)閲� | 519.0 |
閭忚集鍠厓鏁�(sh霉) | 37440.0 |
杓稿嚭鏁�(sh霉)閲� | 409.0 |
绲傜鏁�(sh霉)閲� | 676 |
宄板�煎洖娴佹韩搴� (鈩�) | 250 |
闆绘簮 | 1.2,2.5/3.3 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲-Nom | 1.2V |
瀹夎鏂瑰紡 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
婧害绛夌礆 | 鍟嗘キ(y猫)鎿村睍 |
绲傜瀹屾垚 | 閷�/閵�/閵� (Sn95.5Ag4.0Cu0.5) |
绲傜褰㈠紡 | 鐞� |
绲傜闁撹窛 | 1.0 姣背 |
绲傜浣嶇疆 | 搴曢儴 |
楂樺害 | 2.6 姣背 |
闀峰害 | 27.0 姣背 |
瀵害 | 27.0 姣背 |
鍖呴珨鏉愯唱(zh矛) | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呯瓑鏁堜唬纰� | BGA676,26X26,40 |
鍖呰褰㈢媭 | 姝ｆ柟褰� |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 鐒￠墰锛孎(xi脿n)BGA-676 |
RoHS 鐙�鎱�(t脿i) | 绗﹀悎ROHS3 |
婵曟埃鏁忔劅搴� (MSL) | 3(168 灏忔檪) |
XC3SD1800A-5FGG676C绗﹁櫉
XC3SD1800A-5FGG676C鑵冲嵃
XC3SD1800A-5FGG676C灏佽
鍨嬭櫉 | 鍒堕�犲晢 | 鍝佸悕 | 鎻忚堪 |
XC3SD1800A-4FGG676C | 璩介潏鎬� | FPGA鑺墖 | 1.8M Gates37440 Cells667MHz 90nm 1.2V 676Pin FBGA |
XC3SD1800A-4FG676I | 璩介潏鎬� | FPGA鑺墖 | 1.8M Gates37440 Cells 667MHz 90nm 1.2V 676Pin FBGA |
XC3SD1800A-4FGG676I | 璩介潏鎬� | FPGA鑺墖 | 1.8M Gates37440 Cells 667MHz 90nm 1.2V 676Pin FBGA |
