鍨嬭櫉锛歑C2VP70-6FF1517C
銆�銆�灏佽�濓細FFG1517 (1517 寮曡叧)
銆�銆�閫熷害绛夌礆锛�-6
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細70,496 鍊�(g猫) Slice
銆�銆�RAM 瀹归噺锛�5,328 Kb Distributed RAM 鍜� Block RAM
銆�銆�DSP 涔樻硶鍣ㄦ暩(sh霉)閲忥細256 鍊�(g猫) 18x18 涔樻硶鍣�
銆�銆�I/O 鏁�(sh霉)閲忥細936 鍊�(g猫)鐢ㄦ埗鍙�鐢� I/O
銆�銆�鍏�(n猫i)閮ㄦ檪(sh铆)閻樼�＄悊锛�4 鍊�(g猫) DCM (鏁�(sh霉)瀛楁檪(sh铆)閻樼�＄悊妯″��)
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� JTAG
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細宸ユ��(y猫)绱� -40掳C 鑷� +100掳C

1. 楂樻�ц兘 FPGA 鏋舵��(g貌u)锛氬熀浜� Xilinx 鐨勭��浜屼唬 Virtex-II Pro 鎶�琛�(sh霉)锛屾敮鎸侀珮閬�(d谩) 570 MHz 鐨勯亱(y霉n)琛岄牷鐜�銆�
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銆�銆�5. 澶氭ǎ鍖栫殑瀛樺劜鍣ㄨ硣婧愶細鎻愪緵鍒嗗竷寮� RAM 鍜屽�婄媭 RAM 鐨勭祫鍚�锛屼究浜庡��(sh铆)鐝�(xi脿n) FIFO銆佺珐娌栧崁(q奴)鎴栧皬鍨嬬珐瀛樼瓑鍔熻兘銆�
銆�銆�6. 楂樺害闈堟椿鐨� I/O 妯�(bi膩o)婧�(zh菙n)鏀�鎸侊細鍏煎�瑰�氱ó闆诲�撳拰鍗�(xi茅)璀版��(bi膩o)婧�(zh菙n)锛堝�� LVDS銆丠STL銆丼STL 绛夛級锛屼究浜庤垏澶栭儴瑷�(sh猫)鍌欏皪鎺�銆�
銆�銆�7. 鍏�(n猫i)缃�瑾�(di脿o)瑭﹀伐鍏凤細鏀�鎸� Embedded Logic Analyzer 鍜� ChipScope 宸ュ叿锛屾柟渚块��(j矛n)琛屽湪绶氳��(di脿o)瑭﹀拰椹�(y脿n)璀�銆�
銆�銆�8. 鍙�闈犳�ч珮锛氶�氶亷鍤�(y谩n)鏍肩殑娓�瑭︽祦绋�锛岀⒑淇濆湪鎯″姡鐠�(hu谩n)澧冧笅鐨勭┅(w臎n)瀹氭�у拰鍙�闈犳��銆�

1. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鐢ㄤ簬鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙��(j墨)绛夎ō(sh猫)鍌欎腑鐨勪俊铏熻檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
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XC2VP70-5FF1517C
銆�銆�XC2VP70-7FF1517C