鏅傞枔锛�2023/8/7 16:26:24
闁辫畝锛�358
鐢�(ch菐n)鍝佸瀷铏� | XC2V6000-5BF957I |
鎻忚堪 | IC FPGA 684 I/O 957FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-II |
閮ㄥ垎鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.425V~1.575V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 957-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘 | 957-FCBGA(40x40) |
鍩虹(ch菙)閮ㄤ欢铏� | XC2V6000 |
XC2V6000-5BF957I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鐙�鎱�(t脿i) | 鍋滅敘(ch菐n) |
鏅傞悩闋荤巼-鏈�澶у�� | 750.0 MHz |
CLB-Max鐨勭祫鍚堝欢閬� | 0.39 ns |
JESD-30浠ｇ⒓ | S-PBGA-B957 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 2654208 |
CLB鏁�(sh霉)閲� | 8448.0 |
绛夋晥闁�鏁�(sh霉) | 6000000.0 |
杓稿叆鏁�(sh霉)閲� | 684.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 76032.0 |
杓稿嚭鏁�(sh霉)閲� | 684.0 |
绲傜鏁�(sh霉)閲� | 957 |
绲勭箶 | 8448 CLBS锛�6000000 GATES |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
闆绘簮 | 1.5,1.5 / 3.3,3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.5 V |
闆绘簮闆诲-鏈�灏忓�� | 1.425 V |
闆绘簮闆诲-鏈�澶у�� | 1.575 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.27姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 涓夊崄 |
闀峰害 | 40.0姣背 |
瀵害 | 40.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA957,31X31,50 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 40 X 40 MM锛�1.27 MM PITCH锛孧S-034BAU-1锛孎(xi脿n)LIP CHIP锛孊GA-957 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨) |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
XC2V6000-5BF957I绗﹁櫉
XC2V6000-5BF957I鑵冲嵃
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