XA7K160T-1FFG676Q 鏅傞枔锛�2025/5/16 16:07:35 闁辫畝锛�19

XA7K160T-1FFG676Q 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖涓殑涓€鍊嬪瀷铏�銆侫rtix-7 绯诲垪灏堢偤浣庡姛鑰�銆侀珮鎬ц兘瑷�(sh猫)瑷堣€屽劒(y艒u)鍖�锛岄仼鍚堟噳(y墨ng)鐢ㄤ簬閫氫俊銆侀啱(y墨)鐧傛垚鍍�銆佸伐妤�(y猫)鑷嫊鍖栧拰鑸┖鑸ぉ绛夐牁(l菒ng)鍩�銆�
銆€銆€瑭插瀷铏熷叿鏈夎睈瀵岀殑閭忚集璩囨簮鍜� DSP 妯″锛屾敮鎸佸绋珮閫熶覆琛屾帴鍙ｅ拰瀛樺劜鍣ㄦ帴鍙�銆傚畠閲囩敤 28nm 宸ヨ棟鍒堕€�锛屽叿鍌欓珮闆嗘垚搴﹀拰闈堟椿鎬�锛岃兘澶犳豢瓒冲绋京(f霉)闆滅郴绲�(t菕ng)鐨勯渶姹�銆�

鍙冩暩(sh霉)

绯诲垪锛欰rtix-7
銆€銆€鍨嬭櫉锛歑A7K160T-1FFG676Q
銆€銆€灏佽锛欶FG676
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�484
銆€銆€閰嶇疆妯″紡锛歋electMAP, JTAG, SPI
銆€銆€鐢ㄦ埗鍙敤閭忚集鍠厓锛�163K
銆€銆€DSP 鐗囨暩(sh霉)锛�420
銆€銆€鍏�(n猫i)閮� RAM (KB)锛�1580
銆€銆€鏈€澶у伐浣滈牷鐜� (MHz)锛�550
銆€銆€鍔熻€楋紙鍏稿瀷鍊硷級锛�2.5W
銆€銆€宸ヨ棟鍒剁▼锛�28nm
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€闆绘簮闆诲锛�0.9V 鏍稿績闆诲 / 1.0V I/O 闆诲

鐗规€�

XA7K160T-1FFG676Q 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囦綆鍔熻€楃祫鍚�銆傚叾鍩轰簬 28nm High-K Metal Gate 宸ヨ棟锛岀⒑淇濅簡鏇撮珮鐨勬櫠楂旂瀵嗗害鍜屾洿浣庣殑闈滄厠(t脿i)鍔熻€�銆�
銆€銆€鑺墖鍏�(n猫i)闆嗘垚浜嗗ぇ閲忕殑閭忚集鍠厓鍜� DSP Slice锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑淇¤櫉铏曠悊浠诲嫏(w霉)銆傚悓鏅傦紝瀹冮倓鏀寔澶氶仈(d谩) 12 鍊� GTH 鏀剁櫦(f膩)鍣�锛屽彲浠ュ鐝�(xi脿n)楂橀仈(d谩) 12.5Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆€銆€姝ゅ锛孹A7K160T-1FFG676Q 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗛伕闋呬互鍙婂寮风殑瀹夊叏鐗规€�锛屽寘鎷� AES 鍜� RSA 鍔犲瘑鏀寔銆傞€欎娇寰楀畠闈炲父閬╁悎闇€瑕侀珮搴﹀彲闈犳€у拰瀹夊叏鎬х殑鎳�(y墨ng)鐢ㄥ牬鏅€�
銆€銆€鐐轰簡绨″寲闁嬬櫦(f膩)娴佺▼锛孹ilinx 鎻愪緵浜� Vivado Design Suite 鍜岀浉闂�(gu膩n) IP 鏍镐締骞姪宸ョ▼甯揩閫熸惌寤虹郴绲�(t菕ng)鍘熷瀷骞堕€�(j矛n)琛岄璀�銆�

鎳�(y墨ng)鐢�

XA7K160T-1FFG676Q 涓昏鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛氫緥濡傛鍣ㄨ瑕哄拰鏅鸿兘鐩�(ji膩n)鎺ф敐鍍忛牠銆�
銆€銆€2. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎺冩弿鍎€銆丆T 鎺冩弿鍎€绛�銆�
銆€銆€3. 宸ユキ(y猫)鑷嫊鍖栵細鍙法绋嬮倧杓帶鍒跺櫒 (PLC) 鍜岄亱鍕曟帶鍒剁郴绲�(t菕ng)銆�
銆€銆€4. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細灏忓瀷铚傜鍩虹珯銆佸井娉㈠洖鍌宠ō(sh猫)鍌欍€�
銆€銆€5. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈(d谩)绯荤当(t菕ng)銆佽(w猫i)鏄熼€氫俊杓夎嵎銆�
銆€銆€6. 楂橀€熸暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋愶細娓│娓噺鍎€鍣ㄥ拰绉戝(xu茅)瀵﹂骞宠嚭銆�
銆€銆€鐢变簬鍏跺挤澶х殑鎬ц兘鍜屽唬娉涚殑澶栬ō(sh猫)鏀寔锛岄€欐 FPGA 骞句箮鍙互瑕嗚搵鎵€鏈夊皪瑷堢畻鑳藉姏瑕佹眰杓冮珮鐨勫牬鍚�銆�