鏅傞枔锛�2025/4/28 11:22:08
闁辫畝锛�31
XA7A12T-1CSG325Q 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘(ch菐n)鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗�銆傝┎鍨嬭櫉灞簬楂樻�ц兘銆佷綆鍔熻�楃殑 FPGA 鑺墖锛岄仼鍚堜簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆侀啱(y墨)鐧傝ō鍌欏拰娑堣不闆诲瓙绛夐牁鍩熺殑鎳夌敤銆侫rtix-7 绯诲垪閲囩敤 28nm 鍒剁▼宸ヨ棟锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涗互鍙婇珮閫熶覆琛屾帴鍙�銆�
銆�銆�XA7A12T-1CSG325Q 鐗瑰垾閬╃敤浜庨渶瑕侀珮闆嗘垚搴﹀拰闈堟椿鎬х殑瑷▓鍫存櫙锛屽叾灏佽褰㈠紡鐐� CSG锛圕hip Scale Grid锛�锛屽紩鑵虫暩(sh霉)鐐� 325锛屾敮鎸佸绋厤缃伕闋呭拰宸ヤ綔鐠�(hu谩n)澧�銆�
鍨嬭櫉锛歑A7A12T-1CSG325Q
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�FPGA 閭忚集鍠厓鏁�(sh霉)閲忥細绱� 12,000 鍊� CLB
銆�銆�RAM 瀹归噺锛氱磩 360KB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細30
銆�銆�鏈�澶ф檪閻橀牷鐜囷細瓒呴亷 500MHz
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細325
銆�銆�灏佽椤炲瀷锛欳SG (Chip Scale Grid)
銆�銆�渚涢浕闆诲鑼冨湇锛�0.9V 鑷� 1.0V 鏍稿績闆诲锛�1.8V 鎴� 3.3V I/O 闆诲
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�瀛樺劜姊濅欢锛氬共鐕ョ挵(hu谩n)澧�锛岄伩鍏嶉潨闆�
XA7A12T-1CSG325Q 鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細
銆�銆�Artix-7 绯诲垪閲囩敤鍏堥�茬殑 28nm 宸ヨ棟鍒堕��锛屽叿鍌欏崜瓒婄殑鎬ц兘鑸囪兘鏁堟瘮锛岄仼鐢ㄤ簬灏嶅姛鑰楁晱鎰熺殑鎳夌敤銆�
銆�銆�2. 澶氭ǎ鍖栫殑閭忚集璩囨簮锛�
銆�銆�鎻愪緵 12,000 鍊嬮倧杓柈鍏冿紙CLB锛夛紝鑳藉婊胯冻寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗛渶姹�銆�
銆�銆�3. 鍏х疆 DSP Slice锛�
銆�銆�鍖呭惈澶氶仈 30 鍊� DSP Slice锛屾敮鎸侀珮鏁堢殑鏁�(sh霉)瀛搁亱绠楀拰婵炬尝鍣ㄨō瑷�銆�
銆�銆�4. 楂橀�熶覆琛屾帴鍙ｏ細
銆�銆�鏀寔楂橀仈 6.6Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛岄仼鐢ㄤ簬楂橀�熸暩(sh霉)鎿�(j霉)鍌宠几浠诲嫏銆�
銆�銆�5. 灏忓瀷鍖栧皝瑁濓細
銆�銆�閲囩敤 325 寮曡叧鐨� CSG 灏佽锛岄仼鍚堢┖闁撳彈闄愮殑瑷▓鐠�(hu谩n)澧�銆�
銆�銆�6. 闈堟椿鐨勫伐浣滄ā寮忥細
銆�銆�鏀寔澶氱ó鍟熷嫊閰嶇疆妯″紡锛屽寘鎷緸闁冨瓨鍟熷嫊銆丣TAG 涓嬭級绛�锛岀啊鍖栭枊鐧�(f膩)娴佺▼銆�
銆�銆�7. 寤ｆ硾鐨勫伐浣滄韩搴﹁寖鍦嶏細
銆�銆�-40掳C 鑷� +100掳C 鐨勫伐妤�(y猫)绱氭韩搴﹁寖鍦�锛岀⒑淇濆湪妤电鐠�(hu谩n)澧冧笅鍙潬閬嬭銆�
XA7A12T-1CSG325Q 鍦ㄤ互涓嬮牁鍩熸湁寤ｆ硾鐨勬噳鐢細
銆�銆�1. 閫氫俊瑷倷锛�
銆�銆�鐢ㄤ簬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛夌恫(w菐ng)绲¤ō鍌欎腑鐨勬暩(sh霉)鎿�(j霉)铏曠悊鍜屽崝(xi茅)璀拌綁鎻涖��
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細
銆�銆�瀵︾従(xi脿n)閬嬪嫊鎺у埗銆佸鏅傜洠(ji膩n)娓拰寰╅洔绯荤当(t菕ng)闆嗘垚銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細
銆�銆�鏀寔瓒呰伈娉��丆T 鎺冩弿鍎�绛夎ō鍌欎腑鐨勫湒鍍忚檿鐞嗗拰绠楁硶鍔犻��銆�
銆�銆�4. 瑕栭牷铏曠悊锛�
銆�銆�鎳夌敤浜庤闋荤法纰笺�佽В纰煎拰鍦栧舰鍔犻�熶换鍕�銆�
銆�銆�5. 娑堣不闆诲瓙鐢�(ch菐n)鍝侊細
銆�銆�鐐烘櫤鑳藉灞呫�佺劇浜烘绛夌敘(ch菐n)鍝佹彁渚涙牳蹇冭▓绠楄兘鍔�銆�
銆�銆�6. 鑸┖鑸ぉ锛�
銆�銆�鐢变簬鍏跺彲闈犳��锛屽彲鐢ㄤ簬琛�(w猫i)鏄熼�氫俊銆侀琛屾帶鍒剁郴绲�(t菕ng)绛夐牁鍩熴��
XA7A15T-1CSG324I, XA7A25T-1CSG324I
