鏅傞枔锛�2025/5/20 13:54:26
闁辫畝锛�19
EP4SGX180FF35C4N 鏄� Altera锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑涓�娆惧熀浜� Stratix GX 绯诲垪鐨� FPGA 鑺墖銆傝┎绯诲垪鑺墖浠ラ珮鎬ц兘鍜岄珮瀵嗗害閭忚集璩囨簮鐐虹壒榛烇紝閬╃敤浜庨�氫俊銆佸唬鎾�佽粛浜�銆侀啱(y墨)鐧傛垚鍍忎互鍙婃暩(sh霉)鎿�(j霉)铏曠悊绛夊京闆滄噳鐢ㄩ牁鍩熴��
銆�銆�Stratix GX 绯诲垪 FPGA 鎻愪緵浜嗚睈瀵岀殑宓屽叆寮忓瓨鍎插櫒銆丏SP 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒崇敤鎴跺皪楂樺付瀵拰寰╅洔閭忚集瑷▓鐨勯渶姹�銆侲P4SGX180FF35C4N 鍏烽珨鍨嬭櫉琛ㄦ槑鍏舵搧鏈� 180K 鐨勯倧杓柈鍏冩暩(sh霉)閲忥紝灏佽褰㈠紡鐐� FF35锛屽苟鍏锋湁鐗瑰畾鐨� I/O 鍜屾�ц兘绛夌礆銆�
閭忚集鍠厓锛�180K
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�
銆�銆�鏈�澶х敤鎴� I/O 鏁�(sh霉)閲忥細916
銆�銆�灏堢敤鏅傞悩璩囨簮锛�24鍊� PLL
銆�銆�鍏�(n猫i)閮ㄥ祵鍏ュ紡瀛樺劜鍣細7.2 Mb
銆�銆�DSP 妯″鏁�(sh霉)閲忥細360
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽褰㈠紡锛欶F35
銆�銆�渚涢浕闆诲锛�1.2V 鏍稿績锛�1.5V 杓斿姪锛�2.5V I/O
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛�3.125 Gbps
銆�銆�I/O 閵�琛屾暩(sh霉)閲忥細36
EP4SGX180FF35C4N 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓祼(ji茅)妲嬶細鎻愪緵澶氶仈 180K 鐨勯倧杓柈鍏�锛屽彲浠ュ鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 宓屽叆寮� DSP 妯″锛氶泦鎴愪簡 360 鍊嬪皥鐢� DSP 妯″锛屾敮鎸侀珮鎬ц兘鐨勬诞榛為亱绠楀拰淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�3. 鍏�(n猫i)閮ㄥ瓨鍎插櫒璩囨簮锛氶珮閬� 7.2Mb 鐨勫祵鍏ュ紡 RAM锛岃兘澶犲劒(y艒u)鍖栨暩(sh霉)鎿�(j霉)绶╁瓨鍜岃嚚鏅傚瓨鍎查渶姹�銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔 3.125Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鍚堝厜绾栭�氫俊鍜屽叾浠栭渶瑕侀珮甯跺鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�5. 鍙摯灞曠殑 I/O 鎺ュ彛锛氭彁渚� 916 鍊嬬敤鎴跺彲绶ㄧ▼ I/O 寮曡叧锛屾敮鎸佸绋婧栧崝(xi茅)璀板拰鎺ュ彛椤炲瀷銆�
銆�銆�6. 浣庡姛鑰楄ō瑷堬細閫氶亷鍏堥�茬殑闆绘簮绠＄悊鎶�琛擄紝闄嶄綆鏁撮珨鍔熻��锛屽悓鏅備繚鎸侀珮鎬ц兘閬嬭銆�
銆�銆�7. 鏀寔澶氱ó閰嶇疆妯″紡锛氬寘鎷� AS銆丣TAG 鍜岃鍕曚覆琛岀瓑澶氱ó閰嶇疆鏂瑰紡锛屼究浜庣郴绲�(t菕ng)闆嗘垚鑸囪(di脿o)瑭︺��
EP4SGX180FF35C4N 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鍩虹珯鎺у埗鍣�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏍稿績鏁�(sh霉)鎿�(j霉)铏曠悊妯″銆�
銆�銆�2. 楂樼鍦栧儚铏曠悊锛氱敤浜庨啱(y墨)鐧傚奖鍍忚ō鍌�銆佸伐妤�(y猫)瑕栬妾㈡脯绯荤当(t菕ng)涓京闆滅殑鍦栧儚绠楁硶瀵︾従(xi脿n)銆�
銆�銆�3. 杌嶄簨鍙婅埅绌鸿埅澶╋細鍦ㄩ浄閬斾俊铏熻檿鐞�銆佽(w猫i)鏄熼�氫俊绛夐珮鍙潬鎬ц姹傜挵(hu谩n)澧冧腑浣跨敤銆�
銆�銆�4. 鏁�(sh霉)鎿�(j霉)涓績鑸囨湇鍕欏櫒锛氱敤浜庨珮閫熸暩(sh霉)鎿�(j霉)鍖呰檿鐞�銆佺恫(w菐ng)绲″嵏杓夌瓑鍔熻兘銆�
銆�銆�5. 寤ｆ挱瑕栭牷铏曠悊锛氭敮鎸侀珮娓呮垨瓒呴珮娓呰闋绘祦鐨勫鏅傜法纰艰В纰间互鍙婂璺贩闊冲姛鑳�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬姗熷櫒浜烘帶鍒躲�侀亱鍕曟帶鍒朵互鍙婂叾浠栧京闆滅殑宸ユキ(y猫)鎺у埗绯荤当(t菕ng)銆�
EP4SGX230FF35C4N, EP4SGX150FF35C4N
