EP3SL50F780C3N 鏅�(sh铆)闁擄細2023/8/1 11:12:27 闁辫畝锛�467

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鐢�(ch菐n)鍝佸瀷铏�(h脿o)	EP3SL50F780C3N
鎻忚堪	闆嗘垚闆昏矾FPGA 488 I/O 780FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?III L
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	閬�(gu貌)鏅�(sh铆)鐨�
闆诲-闆绘簮	0.86V?1.15V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	780-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	780-FBGA(29x29)
鍩烘湰闆朵欢铏�(h脿o)	EP3SL50

鐢�(ch菐n)鍝佸湒鐗�

EP3SL50F780C3N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)鍏�
鏈€澶ф檪(sh铆)閻橀牷鐜�	717.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B780
JESD-609浠ｇ⒓	1铏�(h脿o)
绺絉AM浣�	2184192
杓稿叆鏁�(sh霉)閲�	488.0
閭忚集鍠厓鏁�(sh霉)	47500.0
杓稿嚭鏁�(sh霉)閲�	488.0
绔瓙鏁�(sh霉)	780
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
闆绘簮	1.2 / 3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.5姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.86浼�
鏈€澶ч浕婧愰浕澹�	0.94浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
闀�(zh菐ng)搴�	29.0姣背
瀵害	29.0姣背
闄勫姞鍔熻兘	瀹冧篃鍙互鍦�1.05鑷�1.15V鐨勯浕婧愯寖鍦嶅収(n猫i)宸ヤ綔
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA780,28X28,40
鍖呰褰㈢媭	寤ｅ牬(ch菐ng)
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	鐒�(w煤)閴汧BGA-780

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒�(w煤)閴涚媭鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒�(w煤)閴�/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

鐗归粸(di菐n)

48,000鑷�338,000鍊�(g猫)绛夋晥閭忚集鍏冪礌(LE)(璜�(q菒ng)鍙冮柋琛�1-1)
2,430鑷�20,497 Kbit鐨勫寮�(qi谩ng)鍨婽riMatrix瀛樺劜(ch菙)鍣�锛岀敱涓夌óRAM濉婂ぇ灏忕祫鎴�锛屽彲瀵�(sh铆)鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜(ch菙)鍣ㄥ拰FIFO绶╂矕鍗€(q奴)
楂橀€烡SP妯″鎻愪緵9脳9銆�12脳12銆�18脳18鍜�36脳36涔樻硶鍣�(鏈€楂�550 MHz)锛屼箻娉曠疮鍔犲姛鑳藉拰鏈夐檺鑴堟矕闊挎噳(y墨ng)(FIR)婵炬尝鍣ㄧ殑灏堢敤瀵�(sh铆)鐝�(xi脿n)
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鍦ㄦ墍鏈塈 / O bank涓婂叿鏈夎嚜鍕�(d貌ng)鏍℃簴(zh菙n)鏀寔鐨勫嫊(d貌ng)鎱�(t脿i)鐗囦笂绲傜(OCT)
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)鍜屽嫊(d貌ng)鎱�(t脿i)鐩镐綅灏�(du矛)婧�(zh菙n)(DPA)闆昏矾鐨勯珮閫熷樊鍒咺 / O鏀寔锛屽彲瀵�(sh铆)鐝�(xi脿n)1.6 Gbps鎬ц兘
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