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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > ZLF645E0P2064G

ZLF645E0P2064G 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2023/8/29 16:20:43 鏌ョ湅 闁辫畝锛�259

椤炲垾锛氶泦鎴愰浕璺� (IC)

鐩寗

姒傝堪

椤炲垾锛氶泦鎴愰浕璺� (IC)
瀹跺涵锛氬祵鍏ュ紡 - 寰帶鍒跺櫒
绯诲垪锛欳rimzon? ZLF
鏍稿績铏曠悊鍣細Z8 LXMC
鑺珨灏哄锛�8-浣�
閫熷害锛�8MHz
閫ｉ�氭�э細UART/USART
澶栧湇瑷�(sh猫)鍌欙細娆犲妾㈡脯/寰�(f霉)浣�锛孒LVD锛孭OR锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛�16
绋嬪簭瀛樺劜鍣ㄥ閲忥細64KB (64K x 8)
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細FLASH
EEPROM 澶�?銆�?
RAM 瀹归噺锛�1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛�1.9 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛�-
鎸暕鍣ㄥ瀷锛�-
宸ヤ綔婧害锛�0掳C ~ 70掳C
灏佽/澶栨锛�20-DIP (0.300", 7.62mm)
鍖呰锛氱浠�
鍏跺畠鍚嶇ū锛�269-4721

zlf645e0p2064g鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

zlf645e0p2064g鍙冩暩(sh霉)

  • 鍒堕�犲晢Maxim Integrated Products
  • 鏍稿績Crimzon
  • 铏曠悊鍣ㄧ郴鍒�ZLF645
  • 鏁�(sh霉)鎿�(j霉)绺界窔瀵害8 bit
  • 鏈�澶ф檪閻橀牷鐜�8 MHz
  • 绋嬪簭瀛樺劜鍣ㄥぇ灏�64 KB
  • 鏁�(sh霉)鎿�(j霉) RAM 澶у皬1 KB
  • 鐗囦笂 ADCNo
  • 宸ヤ綔闆绘簮闆诲2 V to 3.6 V
  • 灏佽 / 绠遍珨PDIP-20
  • 瀹夎棰�(f膿ng)鏍�Through Hole
  • 楂樺害3.68 mm (Max)
  • 鎺ュ彛椤炲瀷UART
  • 闀峰害26.92 mm (Max)
  • 鏈�澶у伐浣滄韩搴�+ 70 C
  • 鏈�灏忓伐浣滄韩搴�0 C
  • 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�40
  • 瀹氭檪鍣ㄦ暩(sh霉)閲�2
  • 灏佽Bulk
  • 绋嬪簭瀛樺劜鍣ㄩ鍨�Flash
  • 宸ュ粻鍖呰鏁�(sh霉)閲�18
  • Supply Voltage - Max3.6 V
  • Supply Voltage - Min2 V
  • 瀵害6.65 mm (Max)