鏅傞枔锛�2025/5/7 22:43:48
闁辫畝锛�24
XQ5VSX95T-2EF1136I 鏄竴娆鹃珮鎬ц兘鐨� FPGA锛堢従鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗�锛屽爆浜� Xilinx 鍏徃鐨� Virtex 绯诲垪銆傝┎绯诲垪鑺墖浠ュ叾楂樺瘑搴﹂倧杓硣婧�銆侀珮閫熶覆琛屾帴鍙ｅ拰寮峰ぇ鐨� DSP 鍔熻兘鑰岃仦鍚�銆傛鍨嬭櫉鏀寔澶氱ó寰╅洔鐨勬噳鐢ㄥ牬鏅�锛屼緥濡傞�氫俊绯荤当(t菕ng)銆佷俊铏熻檿鐞嗐�佸湒鍍忚檿鐞嗕互鍙婂伐妤�(y猫)鑷嫊鍖栫瓑銆傚叾瑷▓鍏佽ū鐢ㄦ埗閫氶亷纭欢鎻忚堪瑾炶█锛堝 Verilog 鎴� VHDL锛夊皪鍏ч儴閭忚集閫茶鑷畾缇╅厤缃��
銆�銆�瑭茶姱鐗囬噰鐢ㄤ簡鍏堥�茬殑宸ヨ棟鎶�琛撳埗閫�锛岃兘澶犳彁渚涘崜瓒婄殑鎬ц兘鍜岃純浣庣殑鍔熻��锛屽悓鏅傛敮鎸佽睈瀵岀殑澶栬ō鎺ュ彛鍜屽祵鍏ュ紡瀛樺劜鍣ㄥ銆�
閭忚集鍠厓鏁革細95000
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel
銆�銆�I/O 鏁搁噺锛�484
銆�銆�宸ヤ綔闆诲锛�1.0V 鏍搁浕澹� / 1.8V I/O 闆诲
銆�銆�灏佽椤炲瀷锛欶G1156
銆�銆�鏈�澶ф檪閻橀牷鐜囷細550 MHz
銆�銆�瀛樺劜鍣ㄨ硣婧愶細24 Mb Block RAM
銆�銆�DSP Slice 鏁搁噺锛�720
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚鐗囦笂闁冨瓨锛岄渶澶栫疆閰嶇疆鍣ㄤ欢
1. 楂樺瘑搴﹂倧杓硣婧愶紝閬╃敤浜庡京闆滅畻娉曞鐝惧拰澶ц(gu墨)妯℃暩鎿氳檿鐞嗐��
銆�銆�2. 鍏х疆澶у閲� Block RAM 鍜屽垎甯冨紡 RAM锛屽劒(y艒u)鍖栦簡鏁告摎绶╁瓨鍜岃檿鐞嗘晥鐜�銆�
銆�銆�3. 鏀寔楂橀仈 550 MHz 鐨勬檪閻橀牷鐜�锛岀⒑淇濋珮鏁堢殑鏁告摎鍚炲悙鑳藉姏銆�
銆�銆�4. 鎻愪緵澶氶仈 720 鍊� DSP Slice锛岄仼鍚堥珮鎬ц兘鏁稿瓧淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�5. 澶氱ó I/O 閰嶇疆閬搁爡锛岄潏娲婚仼閰嶄笉鍚岀殑鎳夌敤鍫存櫙銆�
銆�銆�6. 鏀寔澶氱ó妯欐簴鎺ュ彛鍗旇锛屽寘鎷� PCIe銆丟igabit Ethernet 鍜� RocketIO 绛�銆�
銆�銆�7. 鍏峰倷浣庡姛鑰楁ā寮�锛屽彲鏍规摎闇�姹傚嫊鎱�(t脿i)瑾挎暣鎬ц兘鑸囧姛鑰楀钩琛�銆�
銆�銆�8. 鍙�氶亷 JTAG 鎴栧叾浠栨柟寮忛潏娲诲畬鎴愰厤缃拰瑾胯│銆�
1. 閫氫俊鍩虹瑷柦锛屼緥濡傚熀绔欍�佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁告摎鍖呰檿鐞�銆�
銆�銆�2. 楂橀�熶俊铏熻檿鐞�锛岀敤浜庨浄閬旂郴绲�(t菕ng)銆佽(w猫i)鏄熼�氫俊鍜岄煶闋�/瑕栭牷绶ㄨВ纰�銆�
銆�銆�3. 鍦栧儚铏曠悊闋樺煙锛屼緥濡傞啱(y墨)鐧傛垚鍍忚ō鍌欏拰瀹夐槻鐩�(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒�锛屼緥濡傞亱鍕曟帶鍒跺櫒鍜屾鍣ㄤ汉瑕栬绯荤当(t菕ng)銆�
銆�銆�5. 宓屽叆寮忚▓绠楀钩鑷�锛岀敤浜庡湅闃�銆佽埅绌鸿埅澶╁拰鍏朵粬楂樻�ц兘瑷堢畻鍫存櫙銆�
銆�銆�6. 鏁告摎涓績鍔犻�熷崱锛岀敤浜庢鍣ㄥ缈掓帹鐞嗘垨鏁告摎搴姞閫熴��
XQ5VSX95T-3EF1136I, XC5VLX110T-2FF1136I, XC5VSX95T-3FF1136I
