鍨嬭櫉锛歑CZU7EV-1FBVB900E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�铏曠悊鍣�锛氬洓鏍� ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�FPGA 鏋舵��(g貌u)锛歎ltraScale+
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 276K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 4440
銆�銆�RAM 璩囨簮锛氱磩 35.7 MB
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銆�銆�闆绘簮闆诲�擄細鏍稿績闆诲�� 0.85V锛孖/O 闆诲�� 1.8V/3.3V
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C
銆�銆�灏佽�濓細FBVB
銆�銆�寮曡叧鏁�(sh霉)锛�900

XCZU7EV-1FBVB900E 鐨勪富瑕佺壒鎬у寘鎷�锛�
銆�銆�1. 闆嗘垚闆欐牳 ARM Cortex-R5 瀵︽檪铏曠悊鍣�锛屾敮鎸佺‖瀵︽檪鎳�(y墨ng)鐢�銆�
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銆�銆�3. 鍖呭惈璞愬瘜鐨勫�栬��(sh猫)鎺ュ彛鎺у埗鍣�锛屽�� PCIe Gen3銆乁SB銆丼ATA 鍜� Gigabit Ethernet銆�
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XCZU7EV-1FBVB900E 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚�栬�虹郴绲�(t菕ng)锛屽�傛�熷櫒瑕栬��銆佽嚜鍕曢�曢�涘拰鐒′汉姗�銆�
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XCZU7EG-1FBVB900E
銆�銆�XCZU7EV-2FBVB900E
銆�銆�XCZU7EV-3FBVB900E