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XCZU6EG-1FFVC900E 鏄竴娆惧熀浜� Xilinx UltraScale+ 鏋舵鐨勯珮绔� FPGA 鑺墖锛屽爆浜� Zynq UltraScale+ MPSoC 绯诲垪銆傝┎绯诲垪闆嗘垚浜嗗彲绶ㄧ▼閭忚集銆丄RM 铏曠悊鍣ㄧ郴绲�(t菕ng)浠ュ強灏堢敤纭欢鍔犻�熸ā濉�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆佸祵鍏ュ紡瑕栬銆侀�氫俊鍜屽伐妤�(y猫)鑷嫊鍖栫瓑闋樺煙銆俋CZU6EG 鍏锋湁璞愬瘜鐨� I/O 鍜屾帴鍙ｉ伕闋�锛屾敮鎸佸绋�氫俊鍗�(xi茅)璀帮紝骞舵彁渚涘挤澶х殑瑷堢畻鑳藉姏銆�
鍨嬭櫉锛歑CZU6EG-1FFVC900E
銆�銆�灏佽椤炲瀷锛欶FVC900
銆�銆�鍏ф牳鏋舵锛歎ltraScale+
銆�銆�铏曠悊鍣細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�FPGA 閭忚集鍠厓锛氱磩 127K
銆�銆�RAM 瀹归噺锛�2.8MB
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏ч儴闁冨瓨锛岄渶澶栨帴
銆�銆�I/O 鏁搁噺锛氭渶澶� 1248 鍊嬬敤鎴� I/O
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCZU6EG-1FFVC900E 鎻愪緵浜嗛珮搴﹂泦鎴愮殑鐣版铏曠悊骞宠嚭锛岃瀺鍚堜簡楂樻�ц兘鍙法绋嬮倧杓拰澶氭牳铏曠悊鍣ㄧ郴绲�(t菕ng)銆傚叾闂滈嵉鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘 ARM Cortex-A53 鎳夌敤铏曠悊鍣�锛岄仼鍚堥亱琛屽京闆滄搷浣滅郴绲�(t菕ng)銆�
銆�銆�2. 瀵︽檪鎺у埗铏曠悊鍣� ARM Cortex-R5锛岀⒑淇濅綆寤堕伈浠诲嫏鐨勫煼(zh铆)琛�銆�
銆�銆�3. 鍏х疆 GPU 鍜岃闋荤法瑙ｇ⒓鍠厓锛屾敮鎸� 4K 瑕栭牷铏曠悊銆�
銆�銆�4. 寮峰ぇ鐨� DSP Slice 鏀寔楂樼簿搴︽诞榛為亱绠楀拰淇¤櫉铏曠悊銆�
銆�銆�5. 闆嗘垚鐨勯珮閫熸敹鐧�(f膩)鍣ㄦ敮鎸� PCIe Gen4銆丆CIX 鍜屼互澶恫绛夊绋崝(xi茅)璀�銆�
銆�銆�6. 鎻愪緵闈堟椿鐨勫畨鍏ㄥ暉鍕曞姛鑳�锛屼繚闅滅郴绲�(t菕ng)鍏嶅彈鎯℃剰鏀绘搳銆�
銆�銆�7. 寤ｆ硾鐨勮瑭﹀拰鍒嗘瀽宸ュ叿鏀寔锛岀啊鍖栭枊鐧�(f膩)娴佺▼銆�
XCZU6EG-1FFVC900E 琚唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屼緥濡傛鍣ㄨ瑕�銆佽嚜鍕曢椐涜紨鍔╃郴绲�(t菕ng)銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛屽 5G 灏忓瀷鍩虹珯銆佺恫绲″姞閫熷崱銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栬垏鎺у埗绯荤当(t菕ng)锛屾彁渚涘鏅傛暩鎿氶噰闆嗗拰铏曠悊鑳藉姏銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙紝鐢ㄤ簬鍦栧儚铏曠悊鍜岄珮绱氳ê鏂峰姛鑳�銆�
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銆�銆�6. 楂樼娓│娓噺鍎�鍣紝婊胯冻楂樺付瀵拰浣庡欢閬查渶姹�銆�
XCZU7EV-1FFVC900E
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