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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU47DR-L2FFVE1156I

XCZU47DR-L2FFVE1156I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 13:55:32 鏌ョ湅 闁辫畝锛�39

XCZU47DR-L2FFVE1156I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑楂樻�ц兘 FPGA 鑺墖锛岃┎绯诲垪闆嗘垚浜嗗彲绶ㄧ▼閭忚集銆丄RM 铏曠悊鍣ㄧ郴绲�(t菕ng)浠ュ強澶氱ó纭牳澶栬ō(sh猫)銆傛鍨嬭櫉鍏锋湁寮峰ぇ鐨勮▓绠楄兘鍔涳紝閬╃敤浜庨渶瑕侀珮甯跺鍜屼綆寤堕伈鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�瑭茶姱鐗囬噰鐢ㄤ簡 16nm 鍒剁▼宸ヨ棟锛屽叿鍌欓珮搴︾殑闆嗘垚鎬у拰闈堟椿鎬�锛岃兘澶犳豢瓒抽�氫俊銆佸伐妤�(y猫)銆佽埅绌鸿埅澶╁拰姹借粖绛夐牁(l菒ng)鍩熺殑闇�姹�銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑CZU47DR-L2FFVE1156I
銆�銆�灏佽锛欶FVE1156
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 480K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 6800
銆�銆�BRAM 鏁�(sh霉)閲忥細绱� 2900KB
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�
銆�銆�鏅傞悩绠＄悊锛歁MCM 鍜� PLL
銆�銆�I/O 寮曡叧鏁�(sh霉)锛氱磩 1156
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛氬闆绘簮鍩熻ō(sh猫)瑷�

鐗规��

XCZU47DR-L2FFVE1156I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘 ARM Cortex-A53 鍥涙牳铏曠悊鍣�锛屼富闋诲彲閬� 1.5GHz锛岄仼鍚堥亱琛屽京闆滄搷浣滅郴绲�(t菕ng)鍜屽鏅傛帶鍒朵换鍕�(w霉)銆�
銆�銆�2. 鍏�(n猫i)缃洐鏍� ARM Cortex-R5 瀵︽檪铏曠悊鍣紝鏀寔閹栨妯″紡浠ュ寮峰彲闈犳��銆�
銆�銆�3. 鏀寔澶氱ó鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe Gen3 x8銆乁SB 3.0銆丼ATA 3.0 鍜屽崈鍏嗕互澶恫(w菐ng)绛�锛屾柟渚块�ｆ帴澶栭儴瑷�(sh猫)鍌欍��
銆�銆�4. 閰嶅倷澶у閲忕殑濉� RAM (BRAM) 鍜� DSP Slice锛屽彲鐢ㄤ簬瀵︾従(xi脿n)寰╅洔鐨勪俊铏熻檿鐞嗙畻娉�銆�
銆�銆�5. 鎻愪緵楂樻晥鐨勫姛鑰楃鐞嗘柟妗�锛屽厑瑷辩敤鎴舵牴鎿�(j霉)瀵﹂殯闇�姹傚嫊鎱�(t脿i)瑾�(di脿o)鏁村姛鑰楁按骞炽��
銆�銆�6. 鍙�氶亷 Vivado 瑷�(sh猫)瑷堝浠堕�茶闁嬬櫦(f膩)锛屾敮鎸侀珮灞ゆ缍滃悎 (HLS) 鍜� IP 鏍稿京鐢�锛岄檷浣庨枊鐧�(f膩)闁�妾诲苟鍔犻�熺敘(ch菐n)鍝佷笂甯傛檪闁撱��

鎳夌敤

XCZU47DR-L2FFVE1156I 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂�锛屽 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙绛�锛屾彁渚涢珮鍚炲悙閲忕殑鏁�(sh霉)鎿�(j霉)铏曠悊鑳藉姏銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栬垏鎺у埗锛屼緥濡傛鍣ㄤ汉銆侀亱鍕曟帶鍒跺櫒鍜屽伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)锛岀⒑淇濆鏅傛�у拰鍙潬鎬с��
銆�銆�3. 姹借粖闆诲瓙锛岀敤浜庨珮绱氶椐涜紨鍔╃郴绲�(t菕ng) (ADAS) 鍜屼俊鎭妯傜郴绲�(t菕ng)锛屾敮鎸佸姛鑳藉畨鍏ㄦ婧�銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙紝渚嬪鎴愬儚绯荤当(t菕ng)鍜屾偅鑰呯洠(ji膩n)璀峰剙锛屽埄鐢ㄥ叾寮峰ぇ鐨勫苟琛岃▓绠楄兘鍔涘拰浣庡欢閬茬壒鎬с��
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃�锛屽寘鎷浄閬旂郴绲�(t菕ng)鍜岃(w猫i)鏄熼�氫俊锛屾豢瓒宠嫑鍒荤挵(hu谩n)澧冧笅鐨勫伐浣滆姹�銆�

鏇夸唬鍨嬭櫉

XCZU49DR-L2FFVE1156I, XCZU47D-SFVG1517E

xczu47dr-l2ffve1156i鎺ㄨ枽渚涙噳鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu47dr-l2ffve1156i鐢�(ch菐n)鍝�

xczu47dr-l2ffve1156i鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�244,605.70000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? RFSoC
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
  • 鏍稿績铏曠悊鍣�甯� CoreSight? 鐨勫洓鏍� ARM? Cortex?-A53 MPCore?锛屽付 CoreSight? 鐨勯洐鏍� ARM?Cortex?-R5
  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�1.333GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�930K+ 閭忚集鍠厓
  • 宸ヤ綔婧害-40掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨1156-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳鍟嗗櫒浠跺皝瑁�1156-FCBGA锛�35x35锛�