鏅傞枔锛�2025/4/30 19:05:19
闁辫畝锛�33
XCZU3EG-L1SBVA484I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊嬮珮绔瀷铏�锛岃┎绯诲垪绲愬悎浜� ARM 铏曠悊鍣ㄧ殑鍙法绋嬫�ц垏 FPGA 鐨勯潏娲绘�с�傞�欐鑺墖涓昏闈㈠悜楂樻�ц兘宓屽叆寮忚▓绠楁噳鐢�锛屼緥濡傚伐妤�(y猫)鑷嫊鍖栥�侀�氫俊鍩虹瑷柦銆佹苯杌夾DAS绯荤当(t菕ng)浠ュ強鑸┖鑸ぉ鑸囧湅闃查牁鍩熴��
銆�銆�XCZU3EG 灞簬 Zynq UltraScale+ eMPSoC 绯诲垪锛屽畠闆嗘垚浜嗛洐鏍� ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5 铏曠悊鍣�锛屽悓鏅傞倓鍖呭惈澶у閲忕殑 FPGA 閭忚集璩囨簮銆侀珮閫熸敹鐧�(f膩)鍣ㄥ拰璞愬瘜鐨勫瑷帴鍙ｃ��
宸ヨ棟锛�16nm
銆�銆�FPGA閭忚集鍠厓鏁�(sh霉)锛氱磩200K
銆�銆�ARM铏曠悊鍣細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�瀛樺劜鍣細鏀寔 DDR4/LPDDR4
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂�32.75 Gbps
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O闆诲 1.8V/3.3V
銆�銆�灏佽椤炲瀷锛欶FGA
銆�銆�寮曡叧鏁�(sh霉)锛�484
XCZU3EG-L1SBVA484I 鎻愪緵浜嗗挤澶х殑鐣版铏曠悊鑳藉姏锛屽叾闆欐牳 ARM Cortex-A53 铏曠悊鍣ㄨ矤璨亱琛屾搷浣滅郴绲�(t菕ng)鍜岄珮绱氱畻娉�锛岃�岄洐鏍� ARM Cortex-R5 鍓囬仼鍚堝鏅備换鍕欏拰瀹夊叏闂滈嵉鍨嬫噳鐢�銆�
銆�銆�瑭茶姱鐗囬倓鍏峰倷璞愬瘜鐨勫瑷帴鍙�锛屽寘鎷� PCIe銆乁SB銆丼ATA銆佷互澶恫(w菐ng)绛�锛屽苟涓旀搧鏈夐珮閬� 32.75Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒抽珮甯跺闇�姹傜殑鎳夌敤鍫存櫙銆�
銆�銆�姝ゅ锛孎(xi脿n)PGA 閮ㄥ垎鍏佽ū鐢ㄦ埗鏍规摎(j霉)鍏烽珨闇�姹傚畾鍒剁‖浠跺姞閫熸ā濉婏紝寰炶�屽鐝�(xi脿n)鏇撮珮鐨勬�ц兘鍜屾洿浣庣殑鍔熻��銆傝姱鐗囧収閮ㄩ倓闆嗘垚浜嗗畨鍏ㄥ暉鍕曞姛鑳斤紝纰轰繚绯荤当(t菕ng)鐨勫畨鍏ㄦ��銆�
XCZU3EG-L1SBVA484I 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘瑷堢畻鍜岄潏娲荤‖浠跺姞閫熺殑鍫存櫙涓�銆傚吀鍨嬬殑鎳夌敤闋樺煙鍖呮嫭锛�
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栨帶鍒� - 瀵︾従(xi脿n)寰╅洔鐨勫鏅傛帶鍒跺拰鏁�(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�2. 閫氫俊瑷倷 - 鐢ㄤ簬鍩虹珯銆佽矾鐢卞櫒鍜屽叾浠栫恫(w菐ng)绲″熀绀庤ō鏂�銆�
銆�銆�3. 姹借粖闆诲瓙 - 鏀寔 ADAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛夊拰鑷嫊椐曢鍔熻兘銆�
銆�銆�4. 鑸┖鑸ぉ鑸囧湅闃� - 鎻愪緵楂樺彲闈犳�у拰浣庡欢閬茬殑瑷堢畻骞宠嚭銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍� - 鍔犻�熷湒鍍忚檿鐞嗗拰瑷烘柗鍒嗘瀽銆�
銆�銆�6. 閭婄罚瑷堢畻 - 绲愬悎 AI 鎺ㄧ悊鍜屾暩(sh霉)鎿�(j霉)閲囬泦閫茶鏈湴鍖栨櫤鑳芥焙绛�銆�
XCZU3EG-2FFVB1156E, XCZU3EG-1FFVC1760E
