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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU3EG-2SFVC784E

XCZU3EG-2SFVC784E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/5/7 12:01:46 鏌ョ湅 闁辫畝锛�33

XCZU3EG-2SFVC784E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊�(g猫)鍨嬭櫉锛岃┎绯诲垪闆嗘垚浜� ARM 铏曠悊鍣ㄥ拰 FPGA 鏋舵(g貌u)锛屽叿鏈夐珮鎬ц兘銆侀珮闆嗘垚搴﹀拰闈堟椿鎬с�俋CZU3EG 灞簬 Zynq UltraScale+ MPSoC EG 绯诲垪锛岄仼鐢ㄤ簬宓屽叆寮忚瑕�銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)銆佹苯杌婅紨鍔╅椐涚郴绲�(t菕ng)绛夋噳(y墨ng)鐢ㄩ牁(l菒ng)鍩�銆�
銆�銆�瑭插櫒浠跺熀浜� 16nm FinFET+ 宸ヨ棟鍒堕�狅紝鏀寔澶氱ó鎺ュ彛妯�(bi膩o)婧�(zh菙n)鍜屽崝(xi茅)璀�锛岃兘澶犳豢瓒冲皪瑷�(j矛)绠楁�ц兘鍜屽(sh铆)鏅�(sh铆)铏曠悊鑳藉姏鐨勫毚(y谩n)鏍艰姹傘��

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灏佽锛欶FVC784
銆�銆�宸ヨ棟锛�16nm
銆�銆�I/O 鏁�(sh霉)閲忥細1920
銆�銆�瀛樺劜瀹归噺锛�15.4Mb
銆�銆�PS 鏍稿績锛氶洐鏍� ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�FPGA 鏋舵(g貌u)锛歎ltraScale+
銆�銆�鍔熻�楋細鍏稿瀷鍊肩磩 1W锛堣閰嶇疆鑰屽畾锛�

鐗规��

XCZU3EG-2SFVC784E 鎻愪緵浜嗗挤(qi谩ng)澶х殑鐣版(g貌u)铏曠悊鑳藉姏锛屽叾涓昏鐗归粸(di菐n)鍖呮嫭锛�
銆�銆�1. 闆嗘垚浜嗛洐鏍� ARM Cortex-A53 鎳�(y墨ng)鐢ㄨ檿鐞嗗櫒鍜岄洐鏍� ARM Cortex-R5 瀵�(sh铆)鏅�(sh铆)铏曠悊鍣�锛岄仼鍚堝浠诲嫏(w霉)鍜屽(sh铆)鏅�(sh铆)鎺у埗鍫存櫙銆�
銆�銆�2. FPGA 閮ㄥ垎閲囩敤浜� UltraScale+ 鏋舵(g貌u)锛屾彁渚涙洿楂樼殑閭忚集瀵嗗害鍜屼俊铏熷畬鏁存��銆�
銆�銆�3. 鍏�(n猫i)缃� GPU 鍜岃闋荤法瑙ｇ⒓鍠厓锛屾敮鎸� 4K 瑕栭牷铏曠悊鍜岄’绀鸿几鍑�銆�
銆�銆�4. 鏀寔澶氱ó楂橀�熸帴鍙�锛屼緥濡� PCIe Gen3銆乁SB 3.0銆丼ATA銆佸崈鍏嗕互澶恫(w菐ng)绛�銆�
銆�銆�5. 鎻愪緵璞愬瘜鐨勫瑷�(sh猫)閬搁爡(xi脿ng)锛屽 CAN銆両2C銆丼PI 鍜� UART 鎺ュ彛銆�
銆�銆�6. 鍏�(n猫i)缃姞瀵嗗紩鎿�锛屾敮鎸佸畨鍏ㄥ暉鍕�(d貌ng)鍜屾暩(sh霉)鎿�(j霉)淇濊(h霉)鍔熻兘銆�
銆�銆�閫欎簺鐗规�т娇寰� XCZU3EG-2SFVC784E 鎴愮偤闇�瑕侀珮鎬ц兘鍜岄潏娲绘灦妲�(g貌u)鐨勫祵鍏ュ紡绯荤当(t菕ng)鐨勭悊鎯抽伕鎿�銆�

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XCZU3EG-2SFVC784E 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚瑕猴細鐢ㄤ簬宸ユキ(y猫)鐩告(j墨)銆佹(j墨)鍣ㄨ瑕哄拰瑷�(j矛)绠楁(j墨)瑕栬绯荤当(t菕ng)銆�
銆�銆�2. 姹借粖闆诲瓙锛氭敮鎸侀珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛夈�佷俊鎭妯傜郴绲�(t菕ng)鍜岃粖韬帶鍒舵ā濉�銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栵細瀵�(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑鎺у埗绠楁硶鍜屽(sh铆)鏅�(sh铆)鏁�(sh霉)鎿�(j霉)铏曠悊銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鐢ㄤ簬瓒呰伈娉㈡垚鍍�銆佹偅鑰呯洠(ji膩n)璀�(h霉)鍜屽叾浠栭啱(y墨)鐧傚剙鍣�銆�
銆�銆�5. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細閬╃敤浜庡皬鍨嬪熀绔�銆侀倞绶ｈ▓(j矛)绠楃瘈(ji茅)榛�(di菐n)鍜岀恫(w菐ng)绲�(lu貌)鍔犻�熷崱銆�
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鏇夸唬鍨嬭櫉

XCZU3EV-2FFVG1517E
銆�銆�XCZU3CG-2FFVC1517E
銆�銆�XCZU4EG-2FFVC1517E

xczu3eg-2sfvc784e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児(ji脿)

xczu3eg-2sfvc784e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍�(ji脿)鏍�1 : 锟�6,293.94000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害533MHz锛�600MHz锛�1.3GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�154K+ 閭忚集鍠厓
  • 宸ヤ綔婧害0掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨784-BFBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�784-FCBGA锛�23x23锛�