鏅傞枔锛�2025/5/8 10:20:44
闁辫畝锛�20
XCZU21DR-L1FFVD1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪涓殑楂樻�ц兘 FPGA 鑺墖锛屽熀浜庤嚭绌嶉浕 16nm FinFET 宸ヨ棟鍒堕��銆傝┎绯诲垪鑺墖涓昏闈㈠悜楂樺付瀵�銆佷綆寤堕伈鐨勬噳鐢ㄥ牬鏅�锛屼緥濡傛暩鎿氫腑蹇冨姞閫�銆佺恫绲¤檿鐞�銆佸祵鍏ュ紡瑕栬鍜岄珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛夈�傛鍨嬭櫉鍖呭惈涓�鍊� Zynq UltraScale+ MPSoC 鏋舵锛岄泦鎴愪簡 ARM 铏曠悊鍣�銆佸彲绶ㄧ▼閭忚集鍠厓浠ュ強楂橀�熸敹鐧�(f膩)鍣ㄧ瓑闂滈嵉绲勪欢銆�
銆�銆�XCZU21DR-L1FFVD1156E 鎻愪緵浜嗚睈瀵岀殑鎺ュ彛閬搁爡锛屾敮鎸佸绋�氫俊鍗�(xi茅)璀帮紝骞跺叿鏈夊挤澶х殑瑷堢畻鑳藉姏鍜岄潏娲绘��锛岄仼鍚堥渶瑕佸鏅傛暩鎿氳檿鐞嗗拰寰╅洔绠楁硶鐨勭挵(hu谩n)澧�銆�
宸ヨ棟锛�16nm
銆�銆�鍏ф牳鏁搁噺锛氶洐鏍� ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�閭忚集鍠厓鏁搁噺锛�47K
銆�銆�DSP Slice 鏁搁噺锛�2300
銆�銆�濉奟AM鏁搁噺锛�1380
銆�銆�UltraRAM鏁搁噺锛�28
銆�銆�PCIe Gen3 鏀寔锛歺8
銆�銆�DDR 鍏у瓨鎺у埗鍣細DDR4/DDR3
銆�銆�灏佽椤炲瀷锛欶FVD1156
銆�銆�I/O寮曡叧鏁搁噺锛�1024
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銆�銆�2. 闆嗘垚闆欐牳 ARM Cortex-A53 鎳夌敤铏曠悊鍣ㄥ拰闆欐牳 ARM Cortex-R5 瀵︽檪铏曠悊鍣紝鎻愪緵楂樻晥鐨勭暟妲嬭▓绠楄兘鍔�銆�
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銆�銆�5. 鏀寔澶氱ó閫氫俊鍗�(xi茅)璀帮紝鍖呮嫭 PCIe Gen3銆�10Gb Ethernet 鍜� SATA銆�
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1. 鏁告摎涓績鍔犻�燂細
銆�銆�鐢ㄤ簬姗熷櫒瀛哥繏鎺ㄧ悊銆佽闋昏綁纰煎拰鍏朵粬楂樻�ц兘瑷堢畻浠诲嫏銆�
銆�銆�2. 缍茬怠铏曠悊锛�
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銆�銆�3. 宓屽叆寮忚瑕猴細
銆�銆�鐢ㄤ簬瑷堢畻姗熻瑕虹郴绲�(t菕ng)锛屽鍦栧儚璀樺垾銆佺洰妯欐娓瓑銆�
銆�銆�4. 楂樼礆椐曢杓斿姪绯荤当(t菕ng) (ADAS)锛�
銆�銆�瀵︾従鍌虫劅鍣ㄨ瀺鍚堛�佽矾寰戣(gu墨)鍔冪瓑鍔熻兘銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細
銆�銆�鎺у埗寰╅洔鐨勫伐妤�(y猫)瑷倷锛屾彁楂樼敓鐢㈡晥鐜�銆�
銆�銆�6. 閱�(y墨)鐧傛垚鍍忥細
銆�銆�閫茶瀵︽檪鍦栧儚铏曠悊鍜屽垎鏋�銆�
XCZU28DR-2FFVG1156E, XCZU28DR-2LFFVG1156E, XCZU21ES-L1FFVC1156E
