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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XCZU19EG-3FFVD1760E

XCZU19EG-3FFVD1760E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/29 12:26:41 鏌ョ湅 闁辫畝锛�34

XCZU19EG-3FFVD1760E 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘(ch菐n)鐨勯珮绔� FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛夎姱鐗�锛屽爆浜� Zynq UltraScale+ MPSoC 绯诲垪銆傝┎绯诲垪闆嗘垚浜嗗挤(qi谩ng)澶х殑 ARM Cortex-A53 铏曠悊鍣ㄥ拰瀵�(sh铆)鏅�(sh铆)铏曠悊鍠厓锛圧PU锛�锛屽悓鏅�(sh铆)鍏峰倷楂樺害闈堟椿鐨勫彲绶ㄧ▼閭忚集璩囨簮锛岄仼鍚堢敤浜庨渶瑕侀珮鎬ц兘瑷�(j矛)绠�銆佸(sh铆)鏅�(sh铆)铏曠悊鍜屼綆寤堕伈鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�
銆�銆�閫欐 FPGA 涓昏闈㈠悜閫氫俊銆佸伐妤�(y猫)銆侀啱(y墨)鐧傘�佹苯杌婁互鍙婅埅绌鸿埅澶╃瓑闋�(l菒ng)鍩�锛岃兘澶犳豢瓒冲京(f霉)闆滅郴绲�(t菕ng)灏�(du矛)鎬ц兘銆佸姛鑰楀拰闈堟椿鎬х殑闇�姹�銆�

鍙冩暩(sh霉)

灏佽锛欶FVD1760
銆�銆�閫熷害绛夌礆(j铆)锛�-3
銆�銆�I/O 鏁�(sh霉)閲忥細4272
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 180 钀�(w脿n)鍊�(g猫)
銆�銆�瀛樺劜(ch菙)鍣ㄥ閲忥細楂橀仈(d谩) 68MB 宓屽叆寮� RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 5800 鍊�(g猫)
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V I/O 闆诲

鐗规��

XCZU19EG 鎻愪緵浜嗛潪甯搁珮鐨勯倧杓瘑搴﹀拰 DSP 鎬ц兘锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑淇¤櫉(h脿o)铏曠悊浠诲嫏(w霉)銆�
銆�銆�瀹冨収(n猫i)宓� ARM Cortex-A53 鍜� Cortex-R5 闆欐牳铏曠悊鍣�锛屾敮鎸佸(sh铆)鏅�(sh铆)鎿嶄綔绯荤当(t菕ng)鍜岄�氱敤鎿嶄綔绯荤当(t菕ng)鐨勯亱(y霉n)琛�銆�
銆�銆�姝ゅ锛岃┎鑺墖閭勫叿鏈夐珮甯跺鎺ュ彛锛屽 PCIe Gen3銆丏DR4 鎺у埗鍣�銆佸崈鍏嗕互澶恫(w菐ng)绛夛紝鍙互杓曟澗閫ｆ帴澶栭儴瑷�(sh猫)鍌欐垨缍�(w菐ng)绲�(lu貌)銆�
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銆�銆�瑭� FPGA 鏀寔澶氱ó閰嶇疆妯″紡锛屽寘鎷緸闁冨瓨鍟熷嫊(d貌ng)鎴栭�氶亷(gu貌) JTAG 鎺ュ彛鍔犺級姣旂壒娴併��

鎳�(y墨ng)鐢�

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銆�銆�鐢变簬鍏跺挤(qi谩ng)澶х殑铏曠悊鑳藉姏鍜岃睈瀵岀殑澶栬ō(sh猫)鎺ュ彛锛屽畠闈炲父閬╁悎鐢ㄤ綔绯荤当(t菕ng)鐨勬牳蹇冩帶鍒跺櫒鎴栧崝(xi茅)铏曠悊鍣�锛屼緥濡傚湪闆烽仈(d谩)淇¤櫉(h脿o)铏曠悊銆佸湒鍍忚瓨(sh铆)鍒ャ�佹(j墨)鍣ㄥ(xu茅)缈�(x铆)鎺ㄧ悊绛夊牬(ch菐ng)鏅腑鐧�(f膩)鎻噸瑕佷綔鐢�銆�
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鏇夸唬鍨嬭櫉(h脿o)

XCZU28DR-2FFVG1760E
銆�銆�XCZU15EG-3FFVC1760E
銆�銆�XCZU21S-2FFVC1760E

xczu19eg-3ffvd1760e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xczu19eg-3ffvd1760e鍙冩暩(sh霉)

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  • 鍍�(ji脿)鏍�1 : 锟�108,940.93000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
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  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
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