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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU19EG-1FFVC1760E

XCZU19EG-1FFVC1760E 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 18:29:07 鏌ョ湅 闁辫畝锛�33

XCZU19EG-1FFVC1760E 鏄竴娆剧敱 Xilinx锛堣辰闈堟�濓級鐢熺敘(ch菐n)鐨勯珮绔� FPGA 鑺墖锛屽爆浜� Zynq UltraScale+ MPSoC 绯诲垪銆傝┎绯诲垪鑺墖闆嗘垚浜� ARM 铏曠悊鍣ㄥ収(n猫i)鏍稿拰鍙法绋嬮倧杓硣婧�锛屾敮鎸佸绋噳(y墨ng)鐢ㄥ牬鏅�锛屽寘鎷祵鍏ュ紡瑕栬銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)銆侀�氫俊绯荤当(t菕ng)绛�銆俋CZU19EG 鎻愪緵浜嗗挤澶х殑瑷堢畻鎬ц兘鍜岃睈瀵岀殑澶栬ō(sh猫)鎺ュ彛锛岄仼鍚堥渶瑕侀珮鎬ц兘铏曠悊鍜岄潏娲荤‖浠惰ō(sh猫)瑷堢殑鎳�(y墨ng)鐢ㄣ��

鍙冩暩(sh霉)

鍨嬭櫉锛歑CZU19EG-1FFVC1760E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�灏佽锛欶FG1760
銆�銆�I/O 鏁�(sh霉)閲忥細2248
銆�銆�鐢ㄦ埗鍙敤閭忚集鍠厓鏁�(sh霉)閲忥細绱� 195K
銆�銆�瀛樺劜鍣細22.7Mb BRAM 鍜� 36Mb UltraRAM
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75 Gbps
銆�銆�铏曠悊鍣細鍥涙牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�宸ヨ棟绡�(ji茅)榛烇細16nm FinFET
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C

鐗规��

XCZU19EG 鏄竴娆鹃珮搴﹂泦鎴愮殑 FPGA 鑺墖锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 闆嗘垚鍥涙牳 ARM Cortex-A53 鎳�(y墨ng)鐢ㄨ檿鐞嗗櫒鍜岄洐鏍� ARM Cortex-R5 瀵︽檪铏曠悊鍣�锛屾彁渚涘挤澶х殑閫氱敤瑷堢畻鑳藉姏銆�
銆�銆�2. 鍏�(n猫i)缃� UltraScale 鏋舵(g貌u)鐨� FPGA 閭忚集璩囨簮锛岃兘澶�?q奴)宕縁(xi脿n)楂樺害瀹氬埗鍖栫殑纭欢鍔犻�熷姛鑳�銆�
銆�銆�3. 鏀寔楂橀仈 32.75 Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬楂樺付瀵暩(sh霉)鎿�(j霉)鍌宠几鍫存櫙銆�
銆�銆�4. 鎻愪緵澶у閲忕殑鍏�(n猫i)閮ㄥ瓨鍎茶硣婧�锛屽寘鎷� 22.7Mb 鐨� Block RAM 鍜� 36Mb 鐨� UltraRAM锛屾豢瓒冲京(f霉)闆滅畻娉曠殑鏁�(sh霉)鎿�(j霉)绶╁瓨闇�姹�銆�
銆�銆�5. 鏀寔澶氱ó鎺ュ彛鍗�(xi茅)璀帮紝渚嬪 PCIe Gen4銆乁SB 3.0銆丼ATA 鍜� Gigabit Ethernet锛屾柟渚胯垏澶栭儴瑷�(sh猫)鍌欎簰鑱�(li谩n)銆�
銆�銆�6. 鍏�(n猫i)缃畨鍏ㄦā濉�锛屾敮鎸佸姞瀵嗗拰韬唤椹楄瓑锛岀⒑淇濈郴绲�(t菕ng)鐨勫畨鍏ㄦ��銆�
銆�銆�7. 閲囩敤 16nm FinFET 宸ヨ棟鍒堕��锛屽姛鑰楀劒(y艒u)鍖栧嚭鑹诧紝閬╁悎灏嶅姛鑰楁晱鎰熺殑宓屽叆寮忔噳(y墨ng)鐢ㄣ��

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XCZU19EG 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚瑕猴細濡傛鍣ㄨ瑕�銆佽嚜鍕曢椐涜紨鍔╃郴绲�(t菕ng)涓殑鍦栧儚铏曠悊銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鎺у埗鍜岄珮绮惧害閬嬪嫊鎺у埗銆�
銆�銆�3. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細鍖呮嫭 5G 鍩虹珯銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗熺瓑楂樺付瀵渶姹傚牬鏅�銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝瑷�(sh猫)鍌�銆丆T 鎺冩弿鍎�绛夐渶瑕侀珮鎬ц兘淇¤櫉铏曠悊鐨勫牬鍚堛��
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬 AI 鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)鍒嗘瀽绛変换鍕�(w霉)鐨勭‖浠跺姞閫熴��
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細閬╃敤浜庨珮鍙潬鎬ц姹傜殑杌嶄簨閫氫俊鍜屽皫(d菐o)鑸郴绲�(t菕ng)銆�

鏇夸唬鍨嬭櫉

XCZU17EG-1FFVC1760E
銆�銆�XCZU28DR-2FFVG1760E
銆�銆�XCZU29DR-2FFVG1760E

xczu19eg-1ffvc1760e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu19eg-1ffvc1760e璩囨枡 鏇村>

  • 鍨嬭櫉
  • 鎻忚堪
  • 鍝佺墝
  • 闁辫涓嬭級

xczu19eg-1ffvc1760e鍙冩暩(sh霉)

  • 鐝�(xi脿n)鏈夋暩(sh霉)閲�0鐝�(xi脿n)璨ㄦ煡鐪嬩氦鏈�
  • 鍍规牸1 : 锟�50,407.55000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
  • 鏋舵(g貌u)MCU锛孎(xi脿n)PGA
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
  • 閫熷害500MHz锛�600MHz锛�1.2GHz
  • 涓昏灞��Zynq?UltraScale+? FPGA锛�1143K+ 閭忚集鍠厓
  • 宸ヤ綔婧害0掳C ~ 100掳C锛圱J锛�
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�1760-FCBGA锛�42.5x42.5锛�