鏅傞枔锛�2025/5/10 14:17:45
闁辫畝锛�24
XCZU15EG-L2FFVB1156E 鏄竴娆剧敱 Xilinx锛堣辰闈堟�濓級鐢熺敘(ch菐n)鐨勯珮绔� UltraScale+ 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖鍩轰簬 16nm FinFET 宸ヨ棟鎶�琛�(sh霉)锛岄泦鎴愪簡澶ч噺鐨勯倧杓柈鍏�銆丏SP 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬闇�瑕侀珮鎬ц兘瑷堢畻鍜屽京闆滀俊铏熻檿鐞嗙殑鎳夌敤鍫存櫙銆�
銆�銆�閫欐 FPGA 鎻愪緵浜嗗挤澶х殑鍙法绋嬮倧杓硣婧愬拰闈堟椿鐨� I/O 閰嶇疆锛岃兘澶犳豢瓒抽�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻��銆佸祵鍏ュ紡瑕栬浠ュ強宸ユキ(y猫)鑷嫊鍖栫瓑闋樺煙鐨勫妯ｅ寲闇�姹�銆傚叾灏佽褰㈠紡鐐� FFVB1156锛屽叿鏈夎純楂樼殑寮曡叧瀵嗗害鍜屾暎鐔辨�ц兘銆�
鍨嬭櫉锛歑CZU15EG-L2FFVB1156E
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 408K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細3840
銆�銆�BRAM 鏁�(sh霉)閲忥細1920KB
銆�銆�鍏�(n猫i)閮� Flash锛氱劇
銆�銆�閰嶇疆妯″紡锛氬缃厤缃櫒浠�
銆�銆�I/O Bank 鏁�(sh霉)閲忥細42
銆�銆�鏈�澶у伐浣滈牷鐜囷細瓒呴亷 500MHz
銆�銆�鍔熻�楄寖鍦嶏細鏍规摎(j霉)瑷▓涓嶅悓绱勭偤 10W 鑷� 30W
銆�銆�灏佽褰㈠紡锛欶FVB1156
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 0.85V锛岃紨鍔╅浕澹� 1.0V 鍜� 1.8V
XCZU15EG-L2FFVB1156E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 寮峰ぇ鐨勫彲绶ㄧ▼閭忚集璩囨簮锛屾敮鎸佸京闆滅殑绠楁硶瀵︾従(xi脿n)鍜岀‖浠跺姞閫�銆�
銆�銆�2. 闆嗘垚鏈夐珮鎬ц兘鐨勪覆琛屾敹鐧�(f膩)鍣�锛岄�熺巼楂橀仈 32.75Gbps锛岄仼鍚堥珮閫熸暩(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�3. 鍏�(n猫i)缃� DDR4 鎺у埗鍣紝鏀寔楂橀仈 2400Mbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�4. 鏀寔澶氱ó鎺ュ彛妯欐簴锛屽 PCIe Gen4銆丆CIX 鍜屼互澶恫(w菐ng) MAC銆�
銆�銆�5. 鍏峰倷浣庡欢閬茬壒鎬у拰楂樺悶鍚愰噺鑳藉姏锛岄仼鐢ㄤ簬瀵︽檪铏曠悊浠诲嫏銆�
銆�銆�6. 楂樺害闈堟椿鐨勬灦妲�(g貌u)鍏佽ū鐢ㄦ埗鑷畾缇╁姛鑳芥ā濉�锛屾豢瓒崇壒瀹氭噳鐢ㄩ渶姹傘��
銆�銆�7. 鎻愪緵瀹屾暣鐨勯枊鐧�(f膩)宸ュ叿閺� Vivado锛屾柟渚块�茶瑷▓杓稿叆銆佺稖鍚堛�佸竷灞�甯冪窔鍜岄璀�銆�
銆�銆�8. 鍏�(n猫i)缃殑瀹夊叏鍔熻兘鏀寔鍔犲瘑閰嶇疆鏂囦欢鍔犺級锛岄槻姝� IP 娉勯湶銆�
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬姗熷櫒瀛哥繏鎺ㄧ悊銆佽闋昏綁(zhu菐n)纰煎拰鏁�(sh霉)鎿�(j霉)搴姞閫�銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛氭敮鎸� 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊銆�
銆�銆�3. 宓屽叆寮忚瑕猴細瀵︾従(xi脿n)瀵︽檪鍦栧儚铏曠悊鍜岃▓绠楁瑕栬绠楁硶銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬鎺у埗绯荤当(t菕ng)鐨勫鏅傛暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細鎻愪緵楂樻�ц兘淇¤櫉铏曠悊鑳藉姏锛屾敮鎸佽秴鑱叉尝鍜� MRI 瑷倷銆�
銆�銆�6. 姹借粖闆诲瓙锛氱敤浜� ADAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛変腑鐨勬暩(sh霉)鎿�(j霉)铻嶅悎鍜岃檿鐞嗐��
XCZU15EG-2FFVB1156E
銆�銆�XCZU15EG-3FFVB1156E
銆�銆�XCZU15EV-L2FFVB1156E
