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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU15EG-3FFVB1156E

XCZU15EG-3FFVB1156E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/5/8 10:41:08 鏌ョ湅 闁辫畝锛�25

XCZU15EG-3FFVB1156E 鏄竴娆惧熀浜� Xilinx UltraScale+ 鏋舵(g貌u)鐨勯珮鎬ц兘 FPGA 鑺墖锛屽爆浜� Zynq UltraScale+ MPSoC 绯诲垪銆傝┎鑺墖闆嗘垚浜嗗彲绶ㄧ▼閭忚集銆佽檿鐞嗗櫒绯荤当(t菕ng)浠ュ強澶氱ó纭牳澶栬ō(sh猫)锛岄仼鐢ㄤ簬闇�瑕侀珮瑷�(j矛)绠楁�ц兘鍜屽(sh铆)鏅�(sh铆)铏曠悊鑳藉姏鐨勬噳(y墨ng)鐢ㄥ牬鏅�傚畠鐗瑰垾閬╁悎鐢ㄤ簬宓屽叆寮忚瑕�銆佸伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)銆侀�氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佹苯杌婅嚜鍕�(d貌ng)椐曢杓斿姪绯荤当(t菕ng)绛夐牁(l菒ng)鍩�銆�

鍙冩暩(sh霉)

鍨嬭櫉(h脿o)锛歑CZU15EG-3FFVB1156E
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�鏋舵(g貌u)锛欰RM Cortex-A53 + Cortex-R5
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銆�銆�DDR 鍏�(n猫i)瀛樻帴鍙ｏ細鏀寔 DDR4
銆�銆�瑕栭牷绶ㄧ⒓鍣細H.264/HEVC
銆�銆�PCIe 鎺ュ彛锛欸en3 x8
銆�銆�灏佽褰㈠紡锛欶FVB1156
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�宸ヨ棟鍒剁▼锛�16nm

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鏇夸唬鍨嬭櫉(h脿o)

XCZU15EV-3FFVB1156E
銆�銆�XCZU19EG-3FFVB1760E

xczu15eg-3ffvb1156e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xczu15eg-3ffvb1156e鍙冩暩(sh霉)

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  • 鍍�(ji脿)鏍�1 : 锟�73,425.86000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
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