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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU11EG-2FFVF1517I

XCZU11EG-2FFVF1517I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/5/7 15:13:50 鏌ョ湅 闁辫畝锛�27

XCZU11EG-2FFVF1517I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪鑺墖铻嶅悎浜嗛珮鎬ц兘鍙法绋嬮倧杓�銆丄RM Cortex-A53 铏曠悊鍣ㄥ拰瀵︽檪铏曠悊鍠厓锛岄仼鐢ㄤ簬闇�瑕侀珮瑷堢畻鎬ц兘鍜岄潏娲荤‖浠跺姞閫熺殑鎳�(y墨ng)鐢ㄥ牬鏅�銆俋CZU11EG 閰嶅倷 114 钀�嬮倧杓柈鍏冿紝鏀寔澶氱ó鎺ュ彛妯欐簴锛屽寘鎷� PCIe銆乁SB 鍜� Gigabit Ethernet锛屽苟鍏锋湁寮峰ぇ鐨勪俊铏熻檿鐞嗚兘鍔涖��

鍙冩暩(sh霉)

鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�灏佽锛欶FVF1517
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銆�銆�I/O 鏁�(sh霉)閲忥細2600
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銆�銆�RAM 瀹归噺锛�52MB
銆�銆�DSP 鐗囨暩(sh霉)锛�5800
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細1140K
銆�銆�铏曠悊鍣細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C

鐗规��

XCZU11EG-2FFVF1517I 鎻愪緵浜嗛珮搴﹂泦鎴愮殑鏋舵(g貌u)锛屽寘鍚洐鏍� ARM Cortex-A53 鎳�(y墨ng)鐢ㄨ檿鐞嗗櫒鍜岄洐鏍� ARM Cortex-R5 瀵︽檪铏曠悊鍣�銆傞�欑ó瑷�(sh猫)瑷堜娇寰楀畠鑳藉鍦ㄥ祵鍏ュ紡绯荤当(t菕ng)涓悓鏅傚煼(zh铆)琛岄�氱敤瑷堢畻浠诲嫏(w霉)鍜屽鏅傛帶鍒朵换鍕�(w霉)銆�
銆�銆�鑺墖鍏�(n猫i)鍚ぇ閲� DSP Slice锛屽彲浠ュ鐝�(xi脿n)楂樻晥鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗姛鑳�銆傛澶�锛屽叾 FPGA 鏋舵(g貌u)鍏佽ū鐢ㄦ埗鏍规摎(j霉)闇�姹傚畾鍒剁‖浠跺姞閫熸ā濉�锛屽緸鑰屽劒(y艒u)鍖栫壒瀹氭噳(y墨ng)鐢ㄧ殑鎬ц兘銆�
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XCZU11EG-2FFVF1517I 鑺墖涓昏鎳�(y墨ng)鐢ㄤ簬闇�瑕侀珮鎬ц兘瑷堢畻鑸囬潏娲荤‖浠跺姞閫熺殑鍫存櫙锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屽宸ユキ(y猫)鐩告銆侀啱(y墨)鐧傛垚鍍忚ō(sh猫)鍌欑瓑銆�
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鏇夸唬鍨嬭櫉

XCZU11EG-1FFVF1517E
銆�銆�XCZU11EG-1FFVF1517I
銆�銆�XCZU11ES-2FFVG1517E

xczu11eg-2ffvf1517i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu11eg-2ffvf1517i鍙冩暩(sh霉)

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  • 鍍规牸1 : 锟�56,450.59000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
  • 鍖呰鎵樼洡
  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
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  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
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  • 灏佽/澶栨1517-BBGA锛孎(xi脿n)CBGA
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