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鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU11EG-1FFVF1517E

XCZU11EG-1FFVF1517E 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/28 16:48:58 鏌ョ湅 闁辫畝锛�32

XCZU11EG-1FFVF1517E 鏄竴娆剧敱 Xilinx锛堣辰闈堟�濓級鐢熺敘(ch菐n)鐨勯珮鎬ц兘 FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛�銆傝┎鍨嬭櫉(h脿o)灞簬 Zynq UltraScale+ MPSoC 绯诲垪锛岄泦鎴愪簡 ARM 铏曠悊鍣ㄨ垏 FPGA 鍙法绋嬮倧杓�锛岄仼鍚堜簬闇�瑕侀珮瑷�(j矛)绠楁�ц兘鍜屽(sh铆)鏅�(sh铆)铏曠悊鑳藉姏鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�
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鍙冩暩(sh霉)

绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�鍨嬭櫉(h脿o)锛歑CZU11EG-1FFVF1517E
銆�銆�灏佽锛欶FG1517
銆�銆�I/O 鏁�(sh霉)閲忥細2304
銆�銆�瀛樺劜(ch菙)鍣細6.8Mb Block RAM
銆�銆�DSP Slice锛�1920
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�16nm
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績锛�1.8V I/O

鐗规��

XCZU11EG 鏄竴娆鹃珮搴﹂泦鎴愮殑澶氳檿鐞嗗櫒鐗囦笂绯荤当(t菕ng) (MPSoC)锛屽叾鏍稿績鏋舵(g貌u)鍖呮嫭闆欐牳 ARM Cortex-A53 鍜岄洐鏍� ARM Cortex-R5 铏曠悊鍣�銆傚畠鏀寔澶氱ó鎺ュ彛妯�(bi膩o)婧�(zh菙n)锛屼緥濡� PCIe Gen3銆乁SB 3.0銆丼ATA 鍜屽崈鍏嗕互澶恫(w菐ng)銆�
銆�銆�FPGA 閮ㄥ垎鍩轰簬 UltraScale 鏋舵(g貌u)锛屾彁渚涗簡寮�(qi谩ng)澶х殑淇¤櫉(h脿o)铏曠悊鑳藉姏鍜岄潏娲荤殑纭欢瑷�(sh猫)瑷�(j矛)閬搁爡(xi脿ng)銆傛澶�锛岃┎鑺墖閭勫収(n猫i)缃簡鍔犲瘑寮曟搸鍜屽畨鍏ㄥ暉鍕�(d貌ng)鍔熻兘锛屽寮�(qi谩ng)浜嗙郴绲�(t菕ng)鐨勫畨鍏ㄦ��銆�
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銆�銆�- 楂樻晥鐨勯浕婧愮鐞�

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銆�銆�3. 宓屽叆寮忚瑕猴細鐢ㄤ簬鍦栧儚铏曠悊銆佽▓(j矛)绠楁(j墨)瑕栬鍜屾(j墨)鍣ㄥ(xu茅)缈�(x铆)鎺ㄧ悊銆�
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鏇夸唬鍨嬭櫉(h脿o)

XCZU9EG-1FFVC1517E
銆�銆�XCZU15EG-1FFVF1760E
銆�銆�XCZU7EV-2FFVG1517E

xczu11eg-1ffvf1517e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xczu11eg-1ffvf1517e鍙冩暩(sh霉)

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  • 鍍�(ji脿)鏍�1 : 锟�35,280.40000鎵樼洡
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  • 鐢�(ch菐n)鍝佺媭鎱�(t脿i)鍦ㄥ敭
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  • 闁冨瓨澶у皬-
  • RAM 澶у皬256KB
  • 澶栬ō(sh猫)DMA锛學DT
  • 閫ｆ帴鑳藉姏CANbus锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖2C锛孧MC/SD/SDIO锛孲PI锛孶ART/USART锛孶SB OTG
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