鍨嬭櫉(h脿o)锛歑CVU9P-3FLGA2104E
銆�銆�绯诲垪锛歎ltraScale+
銆�銆�宸ヨ棟锛�16nm FinFET+
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 900K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細5800+
銆�銆�Block RAM 瀹归噺锛氱磩 54Mb
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚澶栭儴閰嶇疆闁冨瓨
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶ф敮鎸� 1040 鍊�(g猫)鐢ㄦ埗 I/O
銆�銆�灏佽�濆舰寮忥細FLGA2104 (2104 寮曡叧)
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細宸ユ��(y猫)绱�(j铆) (-40掳C 鑷� +100掳C)

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銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細鐢ㄤ簬璨�(f霉)杓夊潎琛�銆佹暩(sh霉)鎿�(j霉)澹撶府鍙婂姞瀵嗚В瀵嗙瓑鍔熻兘銆�
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XCVU7P-2FFVC1760E
銆�銆�XCVU13P-2FLGA2577E