鑺�鐗囩郴鍒楋細Virtex UltraScale+ HBM
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�16nm
銆�銆�FPGA鏋舵��(g貌u)锛歎ltraScale+
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 350 钀�鍊嬬郴绲�(t菕ng)閭忚集鍠�鍏�
銆�銆�RAM瀹归噺锛氱磩 89MB 宓屽叆寮忓�奟AM
銆�銆�DSP Slice鏁�(sh霉)閲忥細绱� 8400鍊�
銆�銆�I/O鏁�(sh霉)閲忥細鏈�澶氭敮鎸� 2104 鍊嬬敤鎴禝/O
銆�銆�渚涢浕闆诲�擄細鏍稿績闆诲��1.0V
銆�銆�灏佽�濋�炲瀷锛歀2FLVA
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�HBM瀹归噺锛氭渶楂樻敮鎸� 8GB HBM2
銆�銆�HBM甯跺��锛氶珮閬�(d谩) 460 GB/s

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銆�銆�1. 楂樺瘑搴﹂倧杓�璩囨��锛岄仼鍚堝京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
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銆�銆�3. 澶氶仈(d谩) 8400 鍊� DSP Slice锛岀敤浜庨珮鏁堝�︾��(xi脿n)娴�榛�(di菐n)閬�(y霉n)绠楀拰鐭╅櫍涔樻硶绛夋搷浣�銆�
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銆�銆�5. 鍏�(n猫i)缃�璞愬瘜鐨勫�栬ō(sh猫)鎺ュ彛 IP 鏍�锛屽�� PCIe Gen4銆丆CIX 鍜屼互澶�缍�(w菐ng) MAC銆�
銆�銆�6. 鎻愪緵寮�(qi谩ng)澶х殑瀹夊叏鍔熻兘锛屽寘鎷� AES-256 鍔犲瘑鍜� RSA 绨藉悕椹楄瓑銆�
銆�銆�7. 鏀�鎸佸嫊鎱�(t脿i)鍔熻兘鍒囨彌 (DFX) 鎶�琛�(sh霉)锛屽厑瑷遍儴鍒嗛噸閰嶇疆浠ュ劒(y艒u)鍖栧姛鑰楀拰鎬ц兘銆�
銆�銆�8. 鐗囦笂瑾�(di脿o)瑭﹀拰鍒嗘瀽宸ュ叿闆嗘垚锛屼究浜庨枊鐧�(f膩)鍜岀董璀�(h霉)銆�
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銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細鍙�鐢ㄤ簬鏁�(sh霉)鎿�(j霉)搴�鏌ヨ�㈠姞閫�銆佹暩(sh霉)鎿�(j霉)澹撶府/瑙ｅ�撶府浠ュ強缍�(w菐ng)绲�(lu貌)瀹夊叏铏曠悊銆�
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銆�銆�6. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鏀�鎸侀��(y墨)瀛�(xu茅)褰卞儚閲嶅缓鍜屽�︽檪鏁�(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�鍏堕珮甯跺��瀛樺劜鍣ㄥ拰澶ц��(gu墨)妯″苟琛岃▓绠楄兘鍔涗娇寰楀畠鍦ㄩ渶瑕佸揩閫熸暩(sh霉)鎿�(j霉)铏曠悊鍜屽京(f霉)闆滅畻娉曞煼(zh铆)琛岀殑鍫存櫙涓嬭〃鐝�(xi脿n)鍎�(y艒u)鐣�銆�

XCVU9P-2LFLVA2104E
銆�銆�XCVU5P-2LFLVA2104E