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闁辫畝锛�26
XCVU5P-1FLVC2104E鏄疿ilinx鍏徃鎺ㄥ嚭鐨刄ltraScale+绯诲垪涓殑Virtex UltraScale+ FPGA鍣ㄤ欢銆傝┎绯诲垪FPGA閲囩敤浜嗗厛閫茬殑16nm FinFET鍒堕�犲伐钘�锛屽叿鍌欏挤澶х殑閭忚集璩囨簮銆丏SP鍠厓銆佸瓨鍎插櫒浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆佺恫绲¤檿鐞�銆佷俊铏熻檿鐞嗗拰鏁告摎涓績鍔犻�熺瓑鍫存櫙銆�
銆�銆�姝ゅ瀷铏熷叿楂斿爆浜嶸irtex UltraScale+ HPC锛圚igh Performance Computing锛夊瓙绯诲垪锛岀壒鍒ラ嚌灏嶉珮甯跺鍜岄珮瑷堢畻瀵嗗害閫茶浜嗗劒(y艒u)鍖�銆�
灏佽锛欶LVC2104
銆�銆�閭忚集鍠厓鏁革細绱�350钀郴绲�(t菕ng)閭忚集鍠厓
銆�銆�Block RAM瀹归噺锛殈84Mb
銆�銆�UltraRAM瀹归噺锛殈32Mb
銆�銆�DSP Slice鏁搁噺锛殈9000鍊�
銆�銆�PCIe Gen4鏀寔锛氬閬�8鍊嬬‖鏍告ā濉�
銆�銆�DDR4鏀寔锛氶珮閬�3200 Mbps
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬�32.75 Gbps
銆�銆�IO Bank鏁搁噺锛殈30鍊�
銆�銆�渚涢浕闆诲锛氬闆诲瑷▓锛屽寘鎷�1.0V鏍稿績闆诲锛屼笉鍚孊ank IO闆诲鍙崹绔嬮厤缃�
XCVU5P-1FLVC2104E鎻愪緵浜嗚睈瀵岀殑纭欢璩囨簮鍜岄潏娲荤殑鏋舵瑷▓锛岃兘澶犳豢瓒冲绋京闆滄噳鐢ㄥ牬鏅殑闇�姹�銆傚叾闂滈嵉鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘瑷堢畻鑳藉姏锛氬収閮ㄩ泦鎴愪簡澶ч噺DSP Slice锛屽彲瀵︾従鐭╅櫍閬嬬畻銆丗FT绠楁硶銆佹烤娉㈠櫒瑷▓绛夋暩瀛稿瘑闆嗗瀷浠诲嫏銆�
銆�銆�2. 楂橀�熸暩鎿氬偝杓革細閫氶亷鍏х疆鐨勫閫氶亾楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛屾敮鎸佸CAPI銆丆CIX绛夎妤�(y猫)妯欐簴鍗�(xi茅)璀�锛岄仼鍚堢敤浣滅恫绲℃⿱鎺ユ垨鍔犻�熷崱銆�
銆�銆�3. 澶ц(gu墨)妯＄墖涓婂瓨鍎诧細涓嶅儏鎿佹湁鍌崇当(t菕ng)Block RAM锛岄倓椤嶅寮曞叆浜哢ltraRAM绲愭锛岀偤闇�瑕佸ぇ瀹归噺绶╁瓨鐨勬噳鐢ㄦ彁渚涗究鍒┿��
銆�銆�4. 鍙法绋嬫�у拰闈堟椿鎬э細鐢ㄦ埗鍙互鑷畾缇╅倧杓浕璺締閬╅厤鐗瑰畾闇�姹�锛屽悓鏅傚埄鐢� Vivado Design Suite宸ュ叿閺堥�茶蹇�熼枊鐧�(f膩)鑸囬璀�銆�
銆�銆�5. 纭欢瀹夊叏鐗规�э細鍏у祵鍔犲瘑寮曟搸鍙婅獚璀夊姛鑳斤紝淇濋殰绯荤当(t菕ng)鍦ㄩ亱琛屾湡闁撶殑鏁告摎瀹屾暣鎬ц垏淇濆瘑鎬�銆�
瑭插瀷铏熷唬娉涙噳鐢ㄤ簬澶氬�嬮牁鍩燂紝涓昏鍖呮嫭锛�
銆�銆�1. 鏁告摎涓績锛氫綔鐐烘湇鍕欏櫒鍔犻�熷崱鐨勬牳蹇冪祫浠�锛岀敤浜庡煼(zh铆)琛屾鍣ㄥ缈掓帹鐞�銆佽闋昏綁纰肩瓑宸ヤ綔璨犺級銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛氭湇鍕欎簬5G鍩虹珯寤鸿ō锛岃矤璨熀甯朵俊铏熻檿鐞嗐�佸墠鍌�/鍥炲偝鎺ュ彛绠＄悊绛夊姛鑳�銆�
銆�銆�3. 閱�(y墨)鐧傚奖鍍忚ō鍌欙細鍔╁姏瀵︽檪鍦栧儚閲嶅缓銆佷笁缍覆鏌撶瓑閱�(y墨)鐧傝ê鏂风浉闂滆檿鐞嗕换鍕欍��
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︾従閬嬪嫊杌岃贰瑕�(gu墨)鍔�銆佽瑕烘娓瓑鏅鸿兘鍖栨搷浣�銆�
銆�銆�5. 姹借粖闆诲瓙绯荤当(t菕ng)锛氬弮鑸囬珮绱氶椐涜紨鍔╃郴绲�(t菕ng)鐨勬劅鐭ヨ瀺鍚堥殠娈�锛屾彁楂樿杌婂畨鍏ㄦ�с��
XCVU9P-2FLGA2104E,XCVU7P-2FLGA2104E
