鏅傞枔锛�2025/5/10 15:36:09
闁辫畝锛�28
XCVU3P-2FFVC1517E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛岄噰鐢� 16nm FinFET 宸ヨ棟鍒堕�犮�傝┎鑺墖閬╃敤浜庨珮鎬ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熷拰宓屽叆寮忚瑕虹瓑鎳夌敤闋樺煙銆傚叾楂樺瘑搴﹂倧杓柈鍏冨拰璞愬瘜鐨� I/O 閰嶇疆浣垮叾鎴愮偤闇�瑕佸ぇ瑕�(gu墨)妯℃暩(sh霉)鎿�(j霉)铏曠悊鍜岄珮閫熶簰鑱�(li谩n)鐨勭郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�
銆�銆�瑭插瀷铏熶腑鐨勫叿楂斿惈缇╁涓嬶細XC 琛ㄧず Xilinx 鐨勫晢妤�(y猫)鐢㈠搧锛孷U 琛ㄧず Virtex UltraScale+ 绯诲垪锛�3P 琛ㄧず鍏烽珨 FPGA 瀹舵棌鍜屽閲忕瓑绱�锛�-2 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)FVC1517 琛ㄧず灏佽椤炲瀷鍜屽紩鑵虫暩(sh霉)锛孍 琛ㄧず宸ヤ綔婧害鑼冨湇锛堥�氬父鐐� -40掳C 鑷� +125掳C锛�銆�
閭忚集鍠厓锛氱磩 195 钀�
銆�銆�閰嶇疆瀛樺劜鍣細22 Mbits
銆�銆�DSP 妯″锛�5800 鍊�
銆�銆�Block RAM锛殈52 MB
銆�銆�UltraRAM锛殈36 MB
銆�銆�PCIE 鎺ュ彛锛氭敮鎸� Gen4 x16
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75 Gbps
銆�銆�渚涢浕闆诲锛�0.85V 鏍稿績闆诲
銆�銆�灏佽椤炲瀷锛欶FVC1517
銆�銆�寮曡叧鏁�(sh霉)锛�1517
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +125掳C
XCVU3P-2FFVC1517E 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囬潏娲绘�э紝涓昏鐗归粸鍖呮嫭锛�
銆�銆�1. 楂樺瘑搴﹂倧杓祼妲嬶細鍏х疆杩� 200 钀�嬪彲绶ㄧ▼閭忚集鍠厓锛岄仼鍚堝京闆滅畻娉曞鐝�(xi脿n)銆�
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈 32.75Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勯渶姹�銆�
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細鏁村悎 Block RAM 鍜� UltraRAM锛屾彁渚涚附瑷堣秴閬� 88MB 鐨勭墖涓婂瓨鍎茬┖闁�銆�
銆�銆�4. 寮峰ぇ鐨� DSP 鍔熻兘锛�5800 鍊嬮泦鎴� DSP 妯″锛岀敤浜庢诞榛為亱绠楀拰淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�5. 鏀寔澶氱ó鎺ュ彛妯欐簴锛氬寘鎷� PCIe Gen4銆丆CIX銆丆PRI 绛夊崝(xi茅)璀�锛屼究浜庢寤哄京闆滅殑鐣版绯荤当(t菕ng)銆�
銆�銆�6. 浣庡姛鑰楄ō瑷堬細閫氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鎶�琛撻檷浣庢暣楂旇兘鑰楋紝鎻愰珮鑳芥晥姣�銆�
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細濡傛暩(sh霉)鎿�(j霉)搴煡瑭㈠劒(y艒u)鍖栥�佹鍣ㄥ缈掓帹鐞嗙瓑浠诲嫏銆�
銆�銆�2. 楂樻�ц兘瑷堢畻 (HPC)锛氭敮鎸佺瀛歌▓绠�銆侀噾铻嶅缓妯＄瓑鍫存櫙銆�
銆�銆�3. 缍�(w菐ng)绲″熀绀庤ō鏂斤細5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙鐨勬牳蹇冪祫浠�銆�
銆�銆�4. 宓屽叆寮忚瑕猴細鐢ㄤ簬鑷嫊椐曢銆佸伐妤�(y猫)鑷嫊鍖栦腑鐨勫湒鍍忚檿鐞嗚垏鍒嗘瀽銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細瀵︽檪鍦栧儚閲嶅缓鍜岃檿鐞�銆�
銆�銆�6. 杌嶄簨鑸囪埅澶╋細楂樺彲闈犳�ц姹備笅鐨勪俊铏熻檿鐞嗗拰鎺у埗浠诲嫏銆�
XCVU9P-2FFVA2104E
銆�銆�XCVU7P-2FFVC1517E
銆�銆�XCVU5P-2FFVC1156E
