鏅傞枔锛�2025/5/29 8:45:23
闁辫畝锛�12
XCVU190-FLGA2577 鏄敱 Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽爆浜� Virtex UltraScale+ 绯诲垪涓殑楂樻�ц兘鍨嬭櫉銆傝┎鑺墖閲囩敤浜� 16nm FinFET 宸ヨ棟鍒堕�狅紝闆嗘垚浜嗗ぇ閲忕殑閭忚集鍠厓銆丏SP 妯″銆佸瓨鍎插櫒璩囨簮浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬闇�瑕侀珮瑷堢畻鑳藉姏鍜屽京闆滈倧杓ō瑷堢殑鎳夌敤鍫存櫙銆傛鑺墖閫氬父鐢ㄤ簬鏁�(sh霉)鎿�(j霉)涓績鍔犻��銆佺恫(w菐ng)绲¤檿鐞�銆侀珮绱氫俊铏熻檿鐞嗐�佸湒鍍忚檿鐞嗙瓑楂樻�ц兘瑷堢畻闋樺煙銆�
鍨嬭櫉锛歑CVU190-FLGA2577
銆�銆�灏佽锛欶LGA2577
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 190K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 3,990
銆�銆�Block RAM 瀹归噺锛氱磩 84.6MB
銆�銆�UltraRAM 瀹归噺锛氱磩 22MB
銆�銆�PCIe Gen4 鏀寔锛氭敮鎸�
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬� 32.75Gbps
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲鑼冨湇 0.7V~1.8V
XCVU190-FLGA2577 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘��銆�
銆�銆�1. 楂樺瘑搴﹂倧杓柈鍏冨拰 DSP 妯″浣垮叾闈炲父閬╁悎寰╅洔鐨勬暩(sh霉)瀛搁亱绠楀拰淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�2. 闆嗘垚鐨勫ぇ瀹归噺 Block RAM 鍜� UltraRAM 鍙互婊胯冻鏁�(sh霉)鎿�(j霉)瀵嗛泦鍨嬫噳鐢ㄧ殑闇�姹�銆�
銆�銆�3. 楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄦ敮鎸佸绋�氫俊鍗�(xi茅)璀�锛屽 PCIe Gen4銆�100GbE 绛�锛岀偤绯荤当(t菕ng)浜掕伅(li谩n)鎻愪緵浜嗚睈瀵岀殑閬告搰銆�
銆�銆�4. 鍏�(n猫i)缃殑鏅傞悩绠＄悊妯″鍜屼綆鎶栧嫊 PLL 鎻愬崌浜嗙郴绲�(t菕ng)鐨勬檪閻樻�ц兘銆�
銆�銆�5. 澶氱ó鍔熻�楀劒(y艒u)鍖栨妧琛撳彲浠ラ檷浣庢暣楂旈亱琛屽姛鑰�銆�
銆�銆�6. 鏀寔閮ㄥ垎閲嶉厤缃姛鑳�锛屽厑瑷卞湪閬嬭鏅傚嫊鎱�(t脿i)淇敼閮ㄥ垎閭忚集瑷▓锛屾彁鍗囦簡纭欢鐨勫埄鐢ㄧ巼鍜岄潏娲绘��銆�
XCVU190-FLGA2577 寤ｆ硾鎳夌敤浜庨珮鎬ц兘瑷堢畻闋樺煙銆�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛氶�氶亷骞惰铏曠悊鑳藉姏鎻愬崌鏈嶅嫏鍣ㄦ�ц兘銆�
銆�銆�2. 缍�(w菐ng)绲¤檿鐞嗚ō鍌欙細閬╃敤浜庤矾鐢变氦鎻涙銆佺恫(w菐ng)绲″畨鍏ㄨō鍌欑瓑闇�瑕侀珮閫熸暩(sh霉)鎿�(j霉)鍌宠几鍜岃檿鐞嗙殑鍫村悎銆�
銆�銆�3. 楂樼礆淇¤櫉铏曠悊锛氬寘鎷浄閬斻�佽伈鍚跺拰鍏朵粬瀵︽檪淇¤櫉铏曠悊鎳夌敤銆�
銆�銆�4. 鍦栧儚鑸囪闋昏檿鐞嗭細鏀寔楂樺垎杈ㄧ巼鍦栧儚铏曠悊銆佽闋荤法瑙ｇ⒓绛夊姛鑳�銆�
銆�銆�5. 閱�(y墨)鐧傚奖鍍忚ō鍌欙細渚嬪 CT 鎺冩弿鍎�鍜� MRI 瑷倷涓殑鍦栧儚閲嶅缓绠楁硶瀵︾従(xi脿n)銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細鐢ㄤ簬寰╅洔宸ユキ(y猫)鎺у埗绯荤当(t菕ng)涓渶瑕佸揩閫熼熆鎳夌殑浠诲嫏銆�
XCVU160-FLGA2577
銆�銆�XCVU13P-FFVC1517
銆�銆�XCVU3P-FFVC1517
