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XCVU13P-L2FIGD2104E鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex UltraScale+绯诲垪FPGA鑺墖銆傝┎绯诲垪灏堢偤楂樻�ц兘瑷堢畻銆佺恫绲¤檿鐞嗗拰鏁�(sh霉)鎿�(j霉)涓績鍔犻�熺瓑鎳夌敤瑷▓锛岄噰鐢ㄤ簡16nm FinFET宸ヨ棟鎶�琛擄紝鍏锋湁楂橀倧杓瘑搴�銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏鍜屽挤澶х殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔�銆�
銆�銆�姝ゅ瀷铏熶腑鐨勫叿楂斿弮鏁�(sh霉)瀹氱京濡備笅锛歑CVU琛ㄧずVirtex UltraScale+绯诲垪锛�13P琛ㄧず鑺墖鐨勮(gu墨)妯″拰鎬ц兘绛夌礆锛孡2FI浠ｈ〃鍏烽珨鐨勫皝瑁濆拰鏁ｇ啽鐗规��锛孏D2104琛ㄧず寮曡叧閰嶇疆鍜孖/O Bank鍒嗗竷锛孍鍓囬�氬父琛ㄧず鍟嗘キ(y猫)绱氭韩搴﹁寖鍦嶏紙0掳C鑷�85掳C锛夈��
绯诲垪锛歏irtex UltraScale+
銆�銆�宸ヨ棟锛�16nm
銆�銆�鍨嬭櫉锛歑CVU13P-L2FIGD2104E
銆�銆�灏佽锛歀2FIGD2104
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱�200钀�嬬郴绲�(t菕ng)閭忚集鍠厓
銆�銆�DSP Slice鏁�(sh霉)閲忥細绱�7920鍊�
銆�銆�Block RAM瀹归噺锛氱磩68MB
銆�銆�閰嶇疆Flash锛氱劇鍏х疆
銆�銆�鏅傞悩璩囨簮锛氬PLL/MMCM妯″
銆�銆�IO妯欐簴鏀寔锛歀VCMOS, SSTL, HSTL, PCIe绛�
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹�0.85V锛岃紨鍔╅浕澹�1.8V/1.2V
XCVU13P-L2FIGD2104E鍏峰倷浠ヤ笅椤憲鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜嶶ltraScale+鏋舵锛屾敮鎸佹洿楂樻晥鐨勭墖涓婁簰鑱�(li谩n)鍜屾洿澶х殑鏁�(sh霉)鎿�(j霉)鍚炲悙閲�銆�
銆�銆�2. 寮峰ぇ鐨凞SP鍔熻兘锛氬収宓屼簡澶ч噺鍎�(y艒u)鍖栫殑DSP Slice锛岄仼鍚堢敤浜庢诞榛為亱绠�銆丗FT鍜岀煩闄ｄ箻娉曠瓑楂樻�ц兘瑷堢畻浠诲嫏銆�
銆�銆�3. 澶氭ǎ鍖栫殑鎺ュ彛鏀寔锛氭敮鎸侀珮閬�32Gbps鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屽吋瀹筆CIe Gen4銆丆CIX绛夊绋崝(xi茅)璀�銆�
銆�銆�4. 宓屽叆寮忓瓨鍎插櫒锛氭彁渚涘ぇ瀹归噺鐨勫垎甯冨紡RAM鍜屽RAM锛屽彲闈堟椿鍒嗛厤婊胯冻涓嶅悓鎳夌敤鍫存櫙闇�姹�銆�
銆�銆�5. 鍕曟厠(t脿i)鍔熻兘鍒囨彌锛圖FX锛夛細鍏佽ū閮ㄥ垎閲嶉厤缃互瀵︾従(xi脿n)鍕曟厠(t脿i)瑾挎暣纭欢璩囨簮銆�
銆�銆�6. 鍏х疆瀹夊叏鎬э細鏀寔AES-256鍔犲瘑鍜孲HA-3瑾嶈瓑锛屼繚璀稩P鍜岄厤缃暩(sh霉)鎿�(j霉)鐨勫畨鍏ㄦ��銆�
銆�銆�7. 浣庡姛鑰楄ō瑷堬細閫氶亷楂樼礆闆绘簮绠＄悊鎶�琛撻檷浣庢暣楂斿姛鑰�锛屽悓鏅傜董鎸侀珮鎬ц兘琛ㄧ従(xi脿n)銆�
瑭插瀷铏熺殑FPGA寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鍖呮嫭姗熷櫒瀛哥繏鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)搴煡瑭㈠姞閫熷拰缍茬怠瀹夊叏铏曠悊銆�
銆�銆�2. 缍茬怠閫氫俊锛氶仼鐢ㄤ簬5G鐒＄窔鍩虹瑷柦銆佽矾鐢卞櫒銆佷氦鎻涙鍜屾櫤鑳絅IC鍗�銆�
銆�銆�3. 瑕栭牷铏曠悊锛氱敤浜庡鏅傝闋荤法纰艰В纰�銆佸湒鍍忓寮峰拰瑷堢畻姗熻瑕虹畻娉�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鏀寔宸ユキ(y猫)鐗╄伅(li谩n)缍茬恫闂溿�佹鍣ㄤ汉鎺у埗鍜岄亱鍕曟帶鍒�銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉尝鎴愬儚銆丆T鎺冩弿鍎�绛夐珮鎬ц兘閱�(y墨)鐧傚奖鍍忚檿鐞嗙郴绲�(t菕ng)銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細婊胯冻鍤存牸鐠�(hu谩n)澧冭姹備笅鐨勪俊铏熻檿鐞嗗拰闆烽仈绯荤当(t菕ng)鎳夌敤銆�
XCVU13P-2FFVA2104E
銆�銆�XCVU13P-2FLGA2104E
