绯诲垪锛歏irtex UltraScale+
銆�銆�宸ヨ棟锛�16nm
銆�銆�閫熷害绛夌礆(j铆)锛�-3锛堟渶浣庡欢閬诧級
銆�銆�FPGA 瑕�(gu墨)妯★細13P
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 1,972,800 鍊�(g猫)
銆�銆�DSP 妯″�婃��(sh霉)閲忥細5880 鍊�(g猫)
銆�銆�BRAM 鏁�(sh霉)閲忥細1140 鍊�(g猫)
銆�銆�URAM 鏁�(sh霉)閲忥細432 鍊�(g猫)
銆�銆�IO 鏁�(sh霉)閲忥細鏈�澶ф敮鎸� 1728 鍊�(g猫)鐢ㄦ埗 IO
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細鏈�澶ф敮鎸� 120 鍊�(g猫)
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬�(d谩) 32.75Gbps
銆�銆�灏佽�濋�炲瀷锛欶HGB2104
銆�銆�寮曡叧鏁�(sh霉)锛�2104
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��0掳C 鑷� 85掳C

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XCVU13P-2FHGB2104E
銆�銆�XCVU13P-3FFVB2104E
銆�銆�XCVU13P-2FFVB2104E