鏅傞枔锛�2025/6/4 18:01:16
闁辫畝锛�6
XCVU13P-2FHGB2104I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜庡厛閫茬殑 FinFET 宸ヨ棟鎶�琛撳埗閫犮�傝┎鍣ㄤ欢鍏锋湁楂橀倧杓瘑搴�銆佸ぇ瀹归噺鐨勫祵鍏ュ紡瀛樺劜鍣ㄤ互鍙婅睈瀵岀殑 DSP Slice锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熷拰鍦栧儚铏曠悊绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�姝ゅ瀷铏熼噰鐢ㄤ簡 HBM锛圚igh Bandwidth Memory锛夐泦鎴愭妧琛�锛屽緸鑰岄’钁楁彁鍗囦簡鏁�(sh霉)鎿�(j霉)甯跺鎬ц兘锛屽悓鏅傞檷浣庝簡绯荤当(t菕ng)鍔熻��銆傚叾灏佽褰㈠紡鐐� FHGB2104锛岄仼鍚堥渶瑕侀珮搴﹂泦鎴愬拰楂樻晥鑳借〃鐝�(xi脿n)鐨勮ō瑷�銆�
鑺墖绯诲垪锛歎ltraScale+
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�FPGA 閭忚集鍠厓鏁�(sh霉)閲忥細绱� 185 钀�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細~10,240
銆�銆�Block RAM 瀹归噺锛殈68MB
銆�銆�UltraRAM 瀹归噺锛殈43MB
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬� 32.75Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶氭敮鎸� ~1,920
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.85V
銆�銆�灏佽椤炲瀷锛欶HGB2104
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCVU13P-2FHGB2104I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘瑷堢畻鑳藉姏锛氶�氶亷澶ч噺鐨勯倧杓柈鍏冨拰 DSP Slice锛岃兘澶犳豢瓒冲京闆滅畻娉曞拰瀵︽檪淇¤櫉铏曠悊闇�姹�銆�
銆�銆�2. 闆嗘垚 HBM 鎶�琛擄細鍏�(n猫i)缃珮甯跺鍏�(n猫i)瀛橈紝鎻愪緵妤甸珮鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屾笡灏戝皪澶栭儴鍏�(n猫i)瀛樼殑闇�姹�銆�
銆�銆�3. 鍙摯灞曟�у挤锛氭敮鎸佸绋帴鍙ｆ婧�锛屽 PCIe銆佷互澶恫(w菐ng)鍜� CCIX锛屼究浜庢寤洪潏娲荤殑绯荤当(t菕ng)鏋舵銆�
銆�銆�4. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤鍕曟厠(t脿i)鍔熻�楃鐞嗘妧琛擄紝鍙互鏍规摎(j霉)瀵﹂殯璨犺級瑾�(di脿o)鏁村姛鑰楁按骞�锛屾彁鍗囨暣楂旀晥鐜�銆�
銆�銆�5. 瀹夊叏鎬у寮凤細鍏峰倷纭欢鍔犲瘑妯″鍜屽畨鍏ㄥ暉鍕曞姛鑳斤紝纰轰繚绯荤当(t菕ng)鐨勬暩(sh霉)鎿�(j霉)淇濊鍜屽畬鏁存��銆�
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庢湇鍕欏櫒鍔犻�熴�丄I 鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)鍒嗘瀽鍜岃櫅鎿寲绛夊姛鑳姐��
銆�銆�2. 閫氫俊瑷倷锛氭敮鎸� 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑楂橀�熶俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細瀵︾従(xi脿n)瀵︽檪鍦栧儚铏曠悊鍜岃ê鏂峰垎鏋愩��
銆�銆�4. 鑷嫊椐曢锛氬畬鎴愮挵(hu谩n)澧冩劅鐭�銆佽矾寰戣(gu墨)鍔冨拰姹虹瓥鎺у埗绛夐亱绠椾换鍕欍��
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)寰╅洔鐨勯亱鍕曟帶鍒跺拰姗熷櫒浜鸿瑕鸿檿鐞�銆�
XCVU13P-2FLGA2104I
