鍨嬭櫉(h脿o)锛歑CVU13P-1FLGA2577I
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�FPGA绯诲垪锛歏irtex UltraScale+
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 1,980,000 鍊�(g猫)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細~11,640 鍊�(g猫)
銆�銆�鍏�(n猫i)閮ㄥ�奟AM (Kbits)锛殈73,248 Kbits
銆�銆�URAM 鏁�(sh霉)閲忥細~1,320 鍊�(g猫)
銆�銆�鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲忥細~120 鍊�(g猫)
銆�銆�鏈�澶ф敹鐧�(f膩)鍣ㄩ�熺巼锛�32.75 Gbps
銆�銆�灏佽�濋��(l猫i)鍨嬶細FLGA2577
銆�銆�I/O寮曡叧鏁�(sh霉)閲忥細2,577
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel 绛�
銆�銆�鍔熻�楄寖鍦嶏細瑕栧叿楂旇ō(sh猫)瑷�(j矛)鑰屽畾锛屽吀鍨嬪�� ~30W 鑷� >100W

XCVU13P-1FLGA2577I 鎻愪緵浜嗛潪甯搁珮鐨勯倧杓�璩囨簮瀵嗗害鍜� DSP 鎬ц兘锛岄仼鐢ㄤ簬闇�瑕佸ぇ瑕�(gu墨)妯″苟琛岃▓(j矛)绠楃殑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆傚畠鍖呭惈澶ч噺 UltraRAM 妯″��锛屽彲椤�钁楁彁鍗囩墖涓婂瓨鍎�(ch菙)鑳藉姏锛屽悓鏅�(sh铆)闄嶄綆澶栭儴瀛樺劜(ch菙)鍣ㄨí(f菐ng)鍟�(w猫n)寤堕伈銆�
銆�銆�姝ゅ��锛岃┎鑺�鐗囬倓閰嶅倷浜嗗�氱祫楂橀�熸敹鐧�(f膩)鍣�锛岃兘澶犳豢(m菐n)瓒充笉鍚屽崝(xi茅)璀颁笅鐨勬暩(sh霉)鎿�(j霉)鍌宠几闇�姹傘�備緥濡�锛岄�氶亷(gu貌)纭�鏍� PCIe Gen4 鎺у埗鍣ㄥ��(sh铆)鐝�(xi脿n)鏈嶅嫏(w霉)鍣ㄧ礆(j铆)浜掕伅(li谩n)锛屾垨鍒╃敤楂橀仈(d谩) 32G 鐨� SerDes 閫氶亾妲�(g貌u)寤哄厜閫氫俊閺堣矾銆�
銆�銆�鍦ㄩ枊(k膩i)鐧�(f膩)宸ュ叿鏂归潰锛孹ilinx Vivado Design Suite 鎻愪緵浜嗗畬鏁寸殑鏀�鎸�锛屽緸 RTL 绶ㄧ⒓鍒版瘮鐗规祦鐢熸垚鍏ㄦ祦绋嬭�嗚��锛屽悓鏅�(sh铆)閭勬彁渚涗簡 Power Estimator 绛夎紨鍔╁伐鍏蜂締(l谩i)骞�鍔╁伐绋嬪斧鍎�(y艒u)鍖栬ō(sh猫)瑷�(j矛)鍔熻��銆�
銆�銆�灏�(du矛)浜庝汉宸ユ櫤鑳藉拰姗�(j墨)鍣ㄥ��(xu茅)缈�(x铆)闋�(l菒ng)鍩燂紝姝� FPGA 鍙�鐢ㄤ綔娣卞害瀛�(xu茅)缈�(x铆)鎺ㄧ悊寮曟搸锛岄厤鍚� Xilinx DNNDK 宸ュ叿閺堝揩閫熼儴缃叉ā鍨嬨��

瑭插瀷铏�(h脿o)寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細鐢ㄤ簬鏁�(sh霉)鎿�(j霉)搴�(k霉)鏌ヨ��(x煤n)鍎�(y艒u)鍖�銆佸��(sh铆)鏅�(sh铆)鍔犲瘑瑙ｅ瘑鍙婂�撶府绠楁硶绛変换鍕�(w霉)銆�
銆�銆�2. 楂樻�ц兘瑷�(j矛)绠� (HPC)锛氳В姹虹�戝��(xu茅)浠跨湡銆侀噾铻嶅缓妯＄瓑寰�(f霉)闆滄暩(sh霉)瀛�(xu茅)鍟�(w猫n)椤屻��
銆�銆�3. 缍�(w菐ng)绲�(lu貌)鍩虹��(ch菙)瑷�(sh猫)鏂斤細浣滅偤鏍稿績鍣ㄤ欢瀵�(sh铆)鐝�(xi脿n)璺�鐢卞��銆佷氦鎻涙��(j墨)涓�鐨勬祦閲忕�＄悊鍔熻兘銆�
銆�銆�4. 瑕栭牷寤ｆ挱瑷�(sh猫)鍌欙細鏀�鎸佽秴楂樻竻鍦栧儚铏曠悊绠＄��(xi脿n)妲�(g貌u)寤�銆�
銆�銆�5. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栨帶鍒讹細鍩�(zh铆)琛岄倞绶ｇ�� AI 鎺ㄧ悊鎿嶄綔锛屽�炲��(qi谩ng)鐢熺敘(ch菐n)鏁堢巼銆�
銆�銆�6. 閱�(y墨)鐧傚奖鍍忓垎鏋愶細鎻愪緵浣庡欢閬�銆侀珮绮惧害鐨勬暩(sh霉)鎿�(j霉)閬�(y霉n)绠楄兘鍔�銆�

XCVU13P-2FLGA2577I
銆�銆�XCVU13P-3FLGA2577I