鏅傞枔锛�2025/5/8 9:55:33
闁辫畝锛�27
XCVU125-H1FLVB1760E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex UltraScale 绯诲垪楂樼 FPGA 鑺墖銆傝┎绯诲垪灏堢偤楂樻�ц兘瑷堢畻銆佺恫(w菐ng)绲¤檿鐞嗗拰寰╅洔鏁�(sh霉)瀛椾俊铏熻檿鐞嗘噳鐢ㄨō瑷�锛屽叿鏈夋サ楂樼殑閭忚集瀵嗗害銆佽睈瀵岀殑 DSP 璩囨簮浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�銆傛鍨嬭櫉鏀寔楂樺付瀵瓨鍎插櫒锛圚BM锛�锛岄仼鐢ㄤ簬闇�瑕佸ぇ瀹归噺銆侀珮鍚炲悙閲忕殑鍫存櫙銆�
銆�銆�鍏跺皝瑁濆舰寮忕偤 FLVB1760锛岄仼鍚堜簬瑕佹眰鍤存牸鏁ｇ啽鎬ц兘鍜岀穵婀婂竷灞�鐨勬噳鐢ㄧ挵(hu谩n)澧冦��
閭忚集鍠厓锛�125K
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏х疆
銆�銆�IO 鏁�(sh霉)閲忥細1728
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�闆绘簮闆诲锛�0.9V 鏍稿績 / 1.0V 杓斿姪
銆�銆�灏佽椤炲瀷锛欶LVB1760
銆�銆�鏈�澶ф檪閻橀牷鐜囷細瓒呴亷 550 MHz
銆�銆�HBM 瀹归噺锛�8GB (鍏烽珨鍙栨焙浜庣増鏈�)
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75 Gbps
XCVU125-H1FLVB1760E 鎻愪緵浜嗛潪甯稿挤澶х殑纭欢璩囨簮锛屽寘鎷ぇ閲忕殑鍙法绋嬮倧杓柈鍏冦�佸垎甯冨紡 RAM 鍜屽鐙� RAM銆傚畠閭勯泦鎴愪簡澶氱祫楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犲鐝�(xi脿n)楂橀仈 32.75Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勯渶姹傘��
銆�銆�姝ゅ锛岃┎鑺墖鏀寔纭牳铏曠悊鍣ㄧ郴绲�(t菕ng)锛堝 ARM Cortex-A53 澶氭牳铏曠悊鍣級锛屽彲鐢ㄤ簬寰╅洔鐨勫祵鍏ュ紡瑷堢畻浠诲嫏銆�
銆�銆�閲濆皪鍔熻�楀劒(y艒u)鍖�锛岃姱鐗囧叿鍌欏嫊鎱�(t脿i)鍔熻�楄绡�(ji茅)鍔熻兘锛屽厑瑷辩敤鎴舵牴鎿�(j霉)瀵﹂殯璨犺級瑾挎暣閬嬭鐙�鎱�(t脿i)銆�
銆�銆�鍏堕珮甯跺瀛樺劜鍣紙HBM锛夐泦鎴愰�蹭竴姝ユ彁鍗囦簡鍏у瓨瑷晱閫熷害锛屾笡灏戜簡鍌崇当(t菕ng)澶栭儴 DRAM 甯朵締鐨勫欢閬插晱椤�锛岄潪甯搁仼鍚堜汉宸ユ櫤鑳芥帹鐞�銆佸ぇ鏁�(sh霉)鎿�(j霉)鍒嗘瀽绛夊牬鏅�銆�
涓昏鎳夌敤浜庢暩(sh霉)鎿�(j霉)涓績鍔犻�熷崱銆侀珮绱氱恫(w菐ng)绲¤矾鐢卞櫒/浜ゆ彌姗�銆佸湒鍍忚檿鐞嗚垏瑷堢畻姗熻瑕虹郴绲�(t菕ng)銆佺劇绶氬熀绀庤ō鏂斤紙濡� 5G 鍩虹珯锛�銆侀珮鎬ц兘瑷堢畻闋樺煙涓殑鐭╅櫍閬嬬畻鍔犻�熶互鍙婂鏅備俊铏熻檿鐞嗗钩鑷�銆�
銆�銆�鐢变簬鍏跺崜瓒婄殑 I/O 鎬ц兘鍜屽苟琛岃檿鐞嗚兘鍔�锛屼篃甯歌鐢ㄤ簬闁嬬櫦(f膩)瀹氬埗鍖栫‖浠跺姞閫熻В姹烘柟妗堬紝渚嬪鍩哄洜娓簭鎴栭噾铻嶅缓妯＄瓑闋樺煙銆�
XCVU13P-2FFVB2104E
銆�銆�XCVU9P-2FFVA2104E
